Two-bit Memory Cell with Conductive Charge Segments
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Solution Overview
Problem
Conventional two-bit memory cells using silicon nitride for charge storage have low electron mobility, leading to slow erase speeds when using the Fowler-Nordheim tunneling erase process.
Innovation Solution
A two-bit memory cell design featuring conductive charge storage segments, including silicon-rich nitride or polycrystalline silicon segments, with a nitride segment acting as an electrical insulator between them, and a gate stack structure that includes a control gate and high-k dielectric material to enhance erase speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If silicon nitride layer is used for charge storage, then charge storage capability is provided, but electron mobility is low causing slow erase speed
Solution Approach 1:
The patent employs a composite charge storage structure combining silicon-rich nitride and polycrystalline silicon materials. This composite approach leverages the high electron mobility of polycrystalline silicon while maintaining the charge trapping capability of silicon-rich nitride, thereby achieving fast erase speeds without sacrificing storage reliability
Solution Approach 2:
The patent modifies the material composition parameters of the charge storage layer by creating silicon-rich nitride regions and integrating polycrystalline silicon segments. This parameter change transforms the electrical properties of the charge storage medium, enabling significantly improved electron mobility and erase speed compared to conventional silicon nitride
2Productivity
If conventional silicon nitride charge storage is used, then device structure is simple, but erase process is slow
Solution Approach 1:
The charge storage layer is segmented into distinct functional regions: silicon-rich nitride segments for charge trapping and polycrystalline silicon segments for high-mobility electron transport. This segmentation allows each region to perform its specialized function optimally while collectively achieving fast erase speeds
Solution Approach 2:
The silicon-rich nitride acts as an intermediary between the charge trapping function and the high-mobility polycrystalline silicon regions. It provides the necessary charge storage capability while interfacing with the polycrystalline silicon to enable rapid electron extraction during erase operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design significantly increases erase speed by three to four orders of magnitude compared to conventional cells, utilizing conductive segments for electron storage, which improves electron mobility and facilitates faster data erasure.
Implementation Method 1
The nitride segment electrically insulates the first conductive segment from the second conductive segment
Implementation Method 2
The first and second conductive segments provide respective first and second data bit storage locations in the two-bit memory cell
Implementation Method 3
The two-bit memory cell can be programmed by utilizing hot electron injection and erased by utilizing either a hot hole injection or Fowler-Nordheim tunneling
Data Source
AI summary
According to one exemplary embodiment, a two-bit memory cell includes a gate stack situated over a substrate, where the gate stack includes a charge-trapping layer. The charge-trapping layer includes first and second conductive segments and a nitride segment, where the nitride segment is situated between the first and second conductive segments. The nitride segment electrically insulates the first conductive segment from the second conductive segment. The first and second conductive segments provide respective first and second data bit storage locations in the two-bit memory cell. The gate stack can further include a lower oxide segment situated between the substrate and the charge-trapping layer. The gate stack can further include an upper oxide segment situated over the charge-trapping layer. The gate stack can be situated between a first dielectric segment and a second dielectric segment, where the first and second dielectric segments are situated over respective first and second bitlines.