Two-bit ROM Cell with Alternating Inverted Transistor Configurations
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Solution Overview
Problem
Conventional ROM cells require multiple transistors in series for bit-line discharge, leading to slower discharge rates and increased space requirements, as well as potential inadvertent shorts between adjacent cells.
Innovation Solution
A ROM cell configuration using four n-type transistors connected in series between bit lines and ground, allowing for faster discharge through single transistors and alternating with inverted configurations to minimize space and prevent shorts, while accommodating four bit-pair combinations without unused transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple transistors are connected in series for bit-line discharge, then the discharge path is established, but the discharge rate becomes slower and space requirements increase
Solution Approach 1:
The memory array is divided into alternating first and second memory cells, where first cells use one transistor configuration and second cells use an inverted configuration. This segmentation allows each cell type to discharge through a single transistor path, achieving fast discharge rates while the alternating pattern prevents shorts between adjacent cells.
Solution Approach 2:
The patent employs inverted transistor configurations in alternating memory cells. Specifically, the second memory cells have their transistor connections inverted relative to the first memory cells, which enables both cells to achieve single-transistor discharge paths while the inversion prevents inadvertent shorts between adjacent cells through the complementary bit lines.
2Reliability
If conventional ROM cell configuration is used, then bit storage is achieved, but inadvertent shorts between adjacent cells may occur
Solution Approach 1:
The patent employs inverted transistor configurations in alternating memory cells. Specifically, the second memory cells have their transistor connections inverted relative to the first memory cells, which enables both cells to achieve single-transistor discharge paths while the inversion prevents inadvertent shorts between adjacent cells through the complementary bit lines.
Solution Approach 2:
The memory array is divided into alternating first and second memory cells, where first cells use one transistor configuration and second cells use an inverted configuration. This segmentation allows each cell type to discharge through a single transistor path, achieving fast discharge rates while the alternating pattern prevents shorts between adjacent cells.
3Adaptability or versatility
If four transistors are used per memory cell, then four bit-pair combinations are accommodated, but unused transistors increase space occupancy
Solution Approach 1:
Each memory cell type (first and second) is designed to accommodate all four bit-pair combinations (00, 01, 10, 11) through its transistor configuration and programming, eliminating the need for unused transistors. The alternating inverted configuration ensures that both cell types can represent any bit-pair combination, achieving full versatility without space waste.
Data Source
AI summary
A read-only memory (ROM) cell has first and second transistors connected in series between a true bit line and a voltage reference (e.g., ground), and third and fourth transistors connected in series between a complement bit line and the voltage reference. The gates of the first and third transistors are connected to a first word line, and the gates of the second and fourth transistors are connected to a second word line. The ROM cell is programmed to store any possible combination of two bits of information by appropriately (i) connecting the node between the first and second transistors to either the true bit line, the complement bit line, or the voltage reference and (ii) connecting the node between the third and fourth transistors to either the true bit line, the complement bit line, or the voltage reference.