Two-Buffer Butterfly Processing for Lower Memory Bandwidth
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Solution Overview
Problem
The butterfly process in computing devices requires high memory bandwidth due to the need for simultaneous reading and writing of two data per cycle, which is costly and power-consuming for hardware implementation.
Innovation Solution
A computing device with two buffers and a control unit to optimize data scheduling, allowing alternating storage and retrieval of input data, reducing memory bandwidth requirements while maintaining high hardware utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the butterfly process is implemented with simultaneous reading and writing of two data per cycle, then the transform computation is efficient, but the memory bandwidth requirement becomes very high
Solution Approach 1:
The patent divides the input data into two separate buffers (first buffer and second buffer) that store data in alternating order. This segmentation allows the fetch unit to read from one buffer while the arithmetic unit processes data from the other buffer, effectively halving the memory bandwidth requirement while maintaining the same computational throughput.
Solution Approach 2:
The patent pre-organizes input data in alternating order across two buffers before the transform computation begins. This preliminary arrangement enables the fetch unit to efficiently retrieve consecutive input data without requiring high memory bandwidth during the actual butterfly process, as the data is already positioned for optimal access.
2Quantity of substance
If two buffers are used to store input data in alternating order, then memory bandwidth requirement is reduced, but device complexity increases
Solution Approach 1:
The patent designs the two buffers to be identical in structure and function, with each buffer capable of performing the same data storage and retrieval operations. This universal design simplifies the overall system complexity, as the same buffer architecture can be replicated rather than requiring different complex structures for each buffer.
Solution Approach 2:
The patent combines the functionality of data storage and data scheduling into the buffer structure itself. By integrating the alternating order storage pattern directly into the buffer design, the system eliminates the need for separate complex scheduling logic, thereby reducing overall device complexity while achieving low memory bandwidth requirements.
Data Source
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AI summary
The present application discloses a computing device and a method thereof. The computing device (200) is able to perform a butterfly process upon a sequence of 2N input data. The computing device (200) includes a first buffer (210), a second buffer (220), a fetch unit (230), an arithmetic unit (240), and a control unit (250). The control unit has the fetch unit read 2h input data from a memory as a first group of input data to the first buffer, has the arithmetic unit perform h stages of the butterfly process upon the first group of input data to generate a first group of updated data, has the fetch unit read another 2h input data as a second group of input data to the second buffer when generating the first group of updated data, and has the fetch unit write the first group of updated data to the memory.