Two-by-two pixel structure mitigating signal chain mismatch in CMOS iSoC
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Solution Overview
Problem
CMOS imaging System-on-Chip (iSoC) sensors face challenges in shrinking pixel cell dimensions and column circuitry while maintaining high sensor performance, particularly due to the difficulty in reducing pitch and density of column circuitry, which leads to mismatch issues between signal chains.
Innovation Solution
The implementation of a CMOS imaging system-on-chip (iSoC) sensor using two-by-two pixel structures with shared read buses and multiplexers to select subsets of sampled signals, allowing pixels in one color plane to be read and processed on one side of the chip using a common signal chain and pixels in another color plane to be processed on the opposite side, thereby mitigating signal chain mismatch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If pixel cell dimensions are shrunk to increase device density, then device density is improved, but column circuitry pitch reduction becomes difficult and signal chain mismatch increases
Solution Approach 1:
The pixel array is divided into multiple banks (e.g., four banks), each with its own independent column circuitry and readout path. This segmentation allows each bank to be read out separately through dedicated column buses, effectively doubling the pitch between column circuits while maintaining high device density. The segmentation resolves the contradiction by organizing pixels into groups that can share readout resources without requiring continuous pitch reduction.
Solution Approach 2:
The patent introduces a bank dimension orthogonal to the traditional row-column pixel arrangement. By organizing pixels into banks that are read out through separate column circuits, the design adds a spatial dimension to the readout architecture. This allows column pitch to be effectively doubled in the physical layout while maintaining high pixel density through the bank organization, resolving the pitch reduction difficulty.
2Length of moving object
If column circuitry pitch is reduced to accommodate smaller pixel cells, then pixel cell size is decreased, but signal chain mismatch and performance degradation occur
Solution Approach 1:
By segmenting the pixel array into multiple banks with independent column circuitry, the patent ensures that pixels within each bank share the same signal chain and readout path. This segmentation maintains signal chain matching reliability because all pixels in a bank are processed through identical column circuits and ADCs, eliminating mismatch issues even as pixel cell size decreases.
Solution Approach 2:
The patent merges multiple pixels within each bank to share common column circuitry and readout resources. This merging approach allows smaller pixel cells to be accommodated while maintaining reliable signal chains, as the shared circuitry within each bank ensures consistent signal processing. The merging of pixels into banks with common readout paths resolves the reliability issue.
3Quantity of substance
If device density is increased by shrinking pixel dimensions, then more pixels fit on chip, but column circuitry becomes difficult to shrink and maintain performance
Solution Approach 1:
The patent segments the pixel array into multiple banks, each with its own column circuitry. This segmentation allows the column circuits to be distributed across different regions of the chip, simplifying the layout by eliminating the need to continuously shrink column pitch. The bank structure organizes the complexity into manageable units, making high-density integration more achievable.
Solution Approach 2:
By introducing the bank dimension and organizing pixels into banks that can be read out through separate column circuits, the patent adds spatial organization that simplifies column circuitry layout. This dimensional reorganization allows column circuits to be placed in dedicated regions without requiring continuous pitch reduction, thereby reducing layout complexity while maintaining high pixel density.
4Device complexity
If readout circuits are shared between multiple pixels to reduce complexity, then device complexity is reduced, but pitch in column direction decreases
Solution Approach 1:
The patent segments the pixel array into multiple banks, each with dedicated column circuitry and readout paths. This segmentation allows readout circuits to be shared within banks (reducing overall complexity) while maintaining adequate column pitch, because the bank structure provides spatial separation between column circuits. The segmentation resolves the contradiction by organizing sharing at the bank level rather than at the individual column level.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively doubles the pitch of column circuitry, reduces pixel dimensions, and increases device density while accounting for signal chain mismatch by processing pixels of each color with a common ADC, resulting in improved performance and reduced noise.
Implementation Method 1
each pixel cell in the array can include a photodetector (e.g., photogate, photoconductor, photodiode, ...) that overlays a substrate for yielding a photogenerated charge
Data Source
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AI summary
The claimed subject matter provides systems and/or methods that facilitate mitigating an impact resulting from mismatch between signal chains in a CMOS imaging System-on-Chip (iSoC) sensor. Two-by-two pixel structures can be a basic building block upon which a pixel array is constructed. Further, each two-by-two pixel structure can be associated with a read bus that carries a sampled signal to a top end and a bottom end of a chip. Moreover, multiplexers at either end of the chip can select a subset of the read buses from which to receive a subset of the sampled signals. Accordingly, pixels in a first color plane can be read, processed, etc. on the same side of the chip (e.g., utilizing a common signal chain), while pixels in at least one second color plane can be read, processed, etc. on the other side of the chip (e.g., employing a differing signal chain).