Two-Capacitor DAC With Input Capacitance Compensation
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Solution Overview
Problem
Existing digital-to-analog converters (DACs) using capacitor networks face challenges with size, accuracy, and complexity at high resolutions, particularly due to large numbers of capacitors leading to leakage, mismatch, and parasitic capacitances, which limit their practical implementation.
Innovation Solution
A two-capacitor digital-to-analog converter (2C-DAC) circuit that utilizes a phase and mode controller, redistribution switch, buffer amp, and capacitance compensation circuit to generate an average voltage by coupling two nominally equal capacitors, reducing capacitor mismatch and parasitic capacitance effects, and eliminating the need for calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a capacitor network is used in a DAC, then lower loss is achieved, but large size and poor accuracy at high resolutions occur
Solution Approach 1:
The patent merges multiple capacitor functions into a single capacitor structure. The capacitor serves multiple purposes: storing charge for digital-to-analog conversion, providing feedback capacitance, and enabling both binary-weighted and thermometer-coded operations. This consolidation eliminates the need for multiple separate capacitors, dramatically reducing the overall circuit size while maintaining the low-loss characteristics of capacitor-based DACs.
Solution Approach 2:
The single capacitor in the patent is designed to perform multiple functions simultaneously. It operates as the main storage capacitor for the DAC output, provides feedback capacitance for the operational amplifier, and can be reconfigured through switching to support different resolution modes (binary-weighted or thermometer-coded). This multi-functionality allows the circuit to achieve high resolution without requiring proportionally larger capacitor networks.
2Loss of energy
If a capacitor network is used in a DAC, then lower loss is achieved, but poor accuracy at high resolutions occurs
Solution Approach 1:
By combining multiple capacitor functions into one, the patent eliminates mismatch errors that would arise from having multiple separate capacitors. The single capacitor ensures uniform capacitance values are used throughout the circuit, removing a major source of accuracy degradation in high-resolution DACs. This approach maintains the energy efficiency of capacitor-based designs while achieving the precision needed for high-resolution conversion.
Solution Approach 2:
The patent dynamically changes the effective capacitance values by switching different portions of the single capacitor into or out of the circuit. During the conversion process, the capacitor can be reconfigured to provide different capacitance ratios corresponding to binary-weighted or thermometer-coded schemes. This dynamic parameter adjustment enables high-resolution accurate conversion without requiring a large fixed network of capacitors with tightly controlled values.
3Measurement precision
If a large number of capacitors are used, then high resolution is achieved, but leakage and mismatch increase
Solution Approach 1:
The patent consolidates what would traditionally require multiple capacitors into a single capacitor structure. This eliminates the leakage and mismatch problems inherent in large capacitor networks, as there is only one capacitor to maintain. The single capacitor approach achieves high resolution through temporal multiplexing and switching configurations rather than through parallel capacitor arrays, thereby improving reliability by removing the sources of leakage and mismatch that scale with the number of capacitors.
4Ease of manufacture
If a capacitor network is used, then digital-to-analog conversion is achieved, but calibration is required
Solution Approach 1:
By using a single capacitor for multiple functions including feedback and storage, the patent creates inherently matched capacitance ratios. The feedback capacitance and storage capacitance are physically the same component, ensuring perfect matching without requiring separate calibration procedures. This eliminates the calibration complexity that would otherwise be needed to match multiple separate capacitors, while still achieving accurate digital-to-analog conversion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 2C-DAC achieves high resolution conversion with improved accuracy and reduced size, operating at high resolutions without calibration, suitable for applications requiring low power and high linearity, such as biomedical sensing, while maintaining a simple layout.
Implementation Method 1
a first capacitor and a second capacitor... are configured to charge or discharge the first capacitor or the second capacitor during an input phase and are configured to couple the first capacitor and the second capacitor together during an average phase in order to generate an average voltage
Implementation Method 2
The buffer amp is configured to generate an output voltage based on the average voltage
Implementation Method 3
The capacitance compensation circuit is configured to couple the replica input capacitance to the input capacitance to adjust the average voltage, during the average phase of the conversion process
Data Source
AI summary
A two-capacitor digital-to-analog converter circuit having circuitry to compensate for an unwanted capacitance is disclosed. The converter is configured to generate an average voltage on two capacitors for a sequence of bits in a digital word so that when the final bit is reached, the average voltage corresponds to an analog level of the digital word. The converter is configured to input and average the voltage on the two capacitors using different modes to minimize the effects of capacitor mismatch and switching capacitance on the accuracy of the conversion. The converter includes a buffer amp that has an input capacitance that can affect the conversion. Accordingly, the converter further includes capacitance compensation circuitry configured to provide a replica input capacitance that can be charged and discharged according to the bits of the digital word and coupled to the input capacitor to prevent the input capacitance from affecting the conversion.