Two Channel Bus Architecture Multiplexing Address Data
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Solution Overview
Problem
Conventional bus structures in digital systems require multiple dedicated channels for read, write, and address operations, consuming power and chip area, necessitating a more efficient communication method.
Innovation Solution
A two-channel bus structure where a sending component broadcasts read and write address locations and transfer qualifiers on one channel, allowing the receiving component to store and retrieve data on the same channel, eliminating the need for a separate address channel by using a time division multiplexed 'transmit channel' for address information, data, and transfer qualifiers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bus structures use independent and separate read, write and address channels, then communication between components is standardized and reliable, but the number of dedicated channels increases, consuming more power and chip area
Solution Approach 1:
The patent combines the address channel, read channel, and write channel into a single multiplexed channel. This channel dynamically switches between transmitting address information, read data, and write data based on control signals, thereby reducing the total number of physical channels while maintaining standardized and reliable communication between bus master and bus slave components
Solution Approach 2:
The single multiplexed channel serves multiple functions by sequentially performing address transmission, read data transmission, and write data transmission. The channel is controlled by phase signals that determine its current function, allowing one physical channel to replace what would traditionally require three separate dedicated channels
2Adaptability or versatility
If multiple dedicated channels are used for address, read, and write operations, then communication functionality is comprehensive, but power consumption and chip area increase
Solution Approach 1:
The patent merges multiple dedicated channels into one multiplexed channel that handles address, read, and write operations sequentially. By sharing the same physical channel and its associated driver, receiver, and buffer circuits among multiple functions, the total power consumption and chip area required for these circuits are significantly reduced while maintaining comprehensive communication functionality
3Adaptability or versatility
If multiple dedicated channels are used for address, read, and write operations, then communication functionality is comprehensive, but chip area occupied by driver, receiver and buffer circuits increases
Solution Approach 1:
The patent combines the address channel, read channel, and write channel into a single multiplexed channel, thereby consolidating the driver, receiver, and buffer circuits that would otherwise be required for each separate channel. This sharing of circuits among multiple functions significantly reduces the total chip area occupied by these communication components while preserving full communication functionality
Data Source
AI summary
Various methods and processing systems are disclosed which include sending and receiving components communicating over a bus having first and second channels. The sending component may broadcast on the first channel a plurality of read and write address locations, a plurality of transfer qualifiers, and write data. The receiving component may store the write data broadcast on the first channel at the receiving component based on the write address locations and a first portion of the transfer qualifiers. The receiving component may also retrieve read data from the receiving component based on the read address locations and a second portion of the transfer qualifiers, and broadcast the retrieved read data on the second channel.