Two-Check-Symbol ECC for Single-Symbol Correction and Double-Bit Detection
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Solution Overview
Problem
Existing error correction codes struggle to effectively detect and correct single symbol errors and double bit errors in digital communication and data storage systems, particularly in systems where errors can occur across multiple symbols or bits.
Innovation Solution
The development of error correction codes using a parity check matrix generated based on powers of γ and β, where γ is equal to β raised to the (2m/4−1) power and β is raised to the (2m/2+1) power, with α being a primitive element of Galois Field GF(2m), allowing for the construction of codes that can correct single symbol errors and detect double bit errors, as exemplified by (19, 17) and (18, 16) symbol ECCs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error correction codes are used, then basic error detection capability is provided, but the ability to simultaneously correct single symbol errors and detect double bit errors is insufficient
Solution Approach 1:
The patent changes the mathematical parameters of the code by using a specific parity check matrix constructed from powers of γ and β in Galois Field GF(2^m). This parameter change enables the code to achieve enhanced error detection and correction capabilities while maintaining a systematic structure that is not overly complex
Solution Approach 2:
The patent creates a composite error correction code by combining multiple mathematical structures - specifically integrating the parity check matrix construction method with specific properties of Galois Field elements. This composite approach yields a code that simultaneously achieves single symbol error correction and double bit error detection
2Measurement precision
If more redundant check bits are added to improve error correction capability, then error detection accuracy improves, but the overhead and code length increase
Solution Approach 1:
The patent optimizes the ratio of check bits to data bits by changing the mathematical parameters of the code construction. The specific parity check matrix structure achieves maximum error detection accuracy with minimal redundant bits, avoiding unnecessary code length expansion
Solution Approach 2:
The patent applies partial redundancy strategically - using exactly the number of check bits needed to achieve single symbol error correction and double bit error detection, without adding excessive redundant bits. This partial action approach achieves the required precision without unnecessary overhead
Data Source
AI summary
Systems, apparatuses, and methods for generating error correction codes (ECCs) with two check symbols are disclosed. In one embodiment, a system receives a data word of length N−2 symbols, wherein N is a positive integer greater than 2, wherein each symbol has m bits, and wherein m is positive integer. The system generates a code word of length N symbols from the data word in accordance with a linear code defined by a parity check matrix. The parity check matrix is generated based on powers of γ, wherein γ is equal to β raised to the (2m/4−1) power, β is equal to a raised to the (2m/2+1) power, and α is a primitive element of GF(2m). In another embodiment, the system receives a (N, N−2) code word and decodes the code word by generating a syndrome S from the code word using the parity check matrix.