Two-Chip Semiconductor Storage Layout for High/Low Voltage Isolation

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Solution Overview

Problem

Existing semiconductor storage devices face challenges in optimizing the integration and performance of high voltage and low voltage transistors within a single chip, leading to inefficiencies in power management and operational reliability.

Innovation Solution

The semiconductor storage device is designed with high voltage transistors formed on a first substrate and low voltage transistors on a second substrate, allowing for separate optimization and improved power management through the use of two distinct chips.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If high voltage and low voltage transistors are integrated on a single chip, then device complexity is reduced and area is minimized, but performance optimization and power management efficiency deteriorate due to conflicting design requirements

Engineering Contradiction:

Improvechip integration structureVSAvoidperformance optimization

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The invention divides the semiconductor device into two separate substrates: a first substrate containing high voltage transistors and a second substrate containing low voltage transistors. This segmentation allows each substrate to be independently optimized for its specific voltage requirements, resolving the contradiction between integration and performance optimization by spatially separating conflicting transistor types while maintaining functional connectivity through bonding interfaces.

Inventive Principle:

Principle #1Segmentation

2Ease of manufacture

If high voltage and low voltage transistors are integrated on a single chip, then manufacturing process is simplified, but power management efficiency deteriorates due to inability to separately optimize power consumption

Engineering Contradiction:

Improvemanufacturing processVSAvoidpower consumption

Core Design Contradiction:

Ease of manufactureVSUse of energy by moving object

Solution Approach 1:

The manufacturing process is segmented into separate fabrication steps for high voltage and low voltage transistor substrates, allowing each to be manufactured with optimized processes for its specific requirements. Power management is improved by enabling independent optimization of each substrate's power consumption characteristics, resolving the contradiction between manufacturing simplicity and power efficiency.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Each substrate is designed with local quality optimizations tailored to its specific voltage requirements. The first substrate is optimized for high voltage operation while the second substrate is optimized for low voltage operation, allowing each region to have the appropriate structural and material properties for its function, thereby improving overall power management efficiency.

Inventive Principle:

Principle #3Local quality

3Area of stationary object

If high voltage and low voltage transistors are integrated on a single chip, then device area is minimized, but operational reliability deteriorates due to interference and noise between different voltage domains

Engineering Contradiction:

Improvechip areaVSAvoidoperational reliability

Core Design Contradiction:

Area of stationary objectVSReliability

Solution Approach 1:

The device is segmented into two physically separate substrates, eliminating the interference and noise problems that would occur in a monolithic integration. The first substrate dedicated to high voltage transistors and the second substrate dedicated to low voltage transistors are bonded together, maintaining compact form factor while ensuring operational reliability through physical isolation of voltage domains.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A bonding interface acts as an intermediary between the high voltage and low voltage substrates, providing electrical connection while maintaining physical and electrical isolation. This intermediary structure allows the two voltage domains to communicate necessary signals while preventing interference and noise coupling, thereby ensuring operational reliability.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS12531120B2Semiconductor storage device with transistors of peripheral circuits on two chips

Publication Date: 2026.01.20 KIOXIA CORP

AI summary

A semiconductor storage device includes first and second chips. The first chip includes a first semiconductor substrate, first conductive layers arranged in a first direction and extending in a second direction, a semiconductor column extending in the first direction and facing the first conductive layers, a first charge storage film formed between the first conductive layers and the semiconductor column, a plurality of first transistors on the first semiconductor substrate, and first bonding electrodes electrically connected to a portion of the plurality of first transistors. The second chip includes a second semiconductor substrate, a plurality of second transistors on the second semiconductor substrate, and second bonding electrodes electrically connected to a portion of the plurality of second transistors, and bonded to the first bonding electrodes. A thickness of the second semiconductor substrate in the first direction is smaller than a thickness of the first semiconductor substrate in the first direction.