Two-Die DrMOS Layout for Lower Parasitics and Smaller Area

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Solution Overview

Problem

Current DrMOSs have complex manufacturing processes, high costs, and low integration density due to their die co-package structure, which results in increased area requirements and losses due to parasitic inductance, capacitance, and resistance from excessive leads.

Innovation Solution

The proposed DrMOS structure consists of two dies, one with a drive circuit and a switching transistor, and another with a second switching transistor, connected through a conductor, eliminating the need for additional leads and allowing for flexible selection of transistors based on application needs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a die co-package structure is used with independent dies for drive circuit and switching transistors, then manufacturing flexibility is improved, but device complexity and area increase

Engineering Contradiction:
Improvemanufacturing flexibilityVSAvoidstructure complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent merges the drive circuit and at least one switching transistor into a single integrated die, eliminating the need for separate dies and leads. This integration reduces structural complexity while maintaining manufacturing flexibility through the unified design approach.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If multiple leads are used to connect drive circuit to switching transistors, then electrical connection is improved, but parasitic effects increase

Engineering Contradiction:
Improveelectrical connectionVSAvoidparasitic inductance, capacitance, and resistance
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent extracts and eliminates the leads from the system by integrating the drive circuit and switching transistor directly on the same die. This removal of leads eliminates the source of parasitic inductance, capacitance, and resistance, improving electrical connection quality without harmful parasitic effects.

Inventive Principle:
Principle #2Taking out (Extraction)

3Temperature

If drive circuit and switching transistors are located in different dies, then heat dissipation is improved, but integration density decreases

Engineering Contradiction:
Improveheat dissipationVSAvoidintegration density
Core Design Contradiction:
TemperatureVSProductivity

Solution Approach 1:

The patent transitions from a multi-die three-dimensional arrangement to a planar integration on a single die. This dimensional change allows the drive circuit and switching transistors to be closely integrated in two dimensions, achieving high integration density while providing alternative heat dissipation pathways through the substrate and packaging structure.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12334913B2DrMOS, integrated circuit, electronic device, and preparation method
Publication Date: 2025.06.17 HUAWEI TECH CO LTD
  • US12334913B2 patent drawing
  • US12334913B2 patent drawing
  • US12334913B2 patent drawing

AI summary

A driver metal-oxide-semiconductor field-effect transistor DrMOS, an integrated circuit, an electronic device, and a preparation method are provided. The DrMOS mainly includes a first die and a second die. The first die includes a drive circuit and a first switching transistor, and the drive circuit is connected to a gate of the first switching transistor. The second die includes a second switching transistor, and the drive circuit is connected to a gate of the second switching transistor through a first conductor. The drive circuit and the first switching transistor are prepared in a same die. This helps to reduce an area, loss, and costs of the DrMOS. The first switching transistor and the second switching transistor are prepared in different dies that reduces type selection limitation.