Two-Die SoC Architecture for Hardware Fault Tolerance

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Solution Overview

Problem

Current systems for achieving Safety Integration Levels (SIL) and Hardware Fault Tolerance (HFT) in functional safety applications are complex and costly, requiring additional hardware and skills, and often involve redundant processing channels that are difficult to integrate and certify, especially for higher safety integrity levels.

Innovation Solution

A two-die System on a Chip (SoC) architecture where a primary device with integrated safety monitor and diagnostics is paired with a secondary device, allowing for cross-monitoring and fault tolerance without the need for external Master Control Units, enabling easier integration and reduced complexity by duplicating application execution on both dies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional redundant processing channels are used to achieve SIL and HFT, then functional safety is improved, but device complexity and integration difficulty increase

Engineering Contradiction:

Improvefunctional safetyVSAvoidintegration complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the safety monitor and diagnostics functions directly into the SoC device, merging what were previously separate external components (Master Control Unit) with the processing channels. This integration reduces the number of discrete components and simplifies the overall system architecture while maintaining the redundant processing capability for functional safety.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The SoC device is designed with multi-functionality, where a single device performs both application processing and safety monitoring/diagnostics functions. This universal design eliminates the need for separate dedicated safety components, reducing integration complexity while preserving the functional safety requirements through built-in safety mechanisms.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Difficulty of detecting and measuring

If external Master Control Units are used for safety monitoring, then fault detection capability is improved, but hardware requirements and cost increase

Engineering Contradiction:

Improvefault detection capabilityVSAvoidhardware requirements

Core Design Contradiction:

Difficulty of detecting and measuringVSQuantity of substance

Solution Approach 1:

The safety monitor and diagnostics functions are merged into the SoC device itself, eliminating the need for external Master Control Units. This integration maintains full fault detection capability while reducing the total quantity of hardware components required in the system.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The safety monitoring and diagnostics capabilities are extracted from external separate units and embedded directly within the SoC device. This extraction consolidates hardware resources, reducing the overall component count while preserving the essential fault detection and safety monitoring functions.

Inventive Principle:

Principle #2Taking out (Extraction)

3Reliability

If redundant processing channels are implemented, then hardware fault tolerance is improved, but development time and certification complexity increase

Engineering Contradiction:

Improvehardware fault toleranceVSAvoiddevelopment and certification time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The safety monitor and diagnostics functions are pre-integrated into the SoC device during manufacturing, rather than requiring separate implementation and integration steps during system development. This preliminary action reduces development time and simplifies certification processes by providing ready-to-use safety capabilities that are already configured and tested within the device.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS11360846B2Two die system on chip (SoC) for providing hardware fault tolerance (HFT) for a paired SoC

Publication Date: 2022.06.14 INTEL CORP

AI summary

Apparatuses of systems that provide Safety Integration Levels (SILs) and Hardware Fault Tolerance (HFT) include a first die, the first die including first processing logic connected to a first connection and the first connection connected to second processing logic of a second die. The first die may further include a second connection to an input/output (I/O) channel where the second connection is coupled to the first processing logic. The apparatuses may further include a second die, the second die including second processing logic and a third connection from a secondary device coupled to the second processing logic. The secondary device is outside the system. The second processing logic is configured to select among three configurations based on signals from the second processing logic and the secondary device: sending first output data on the I/O output channel, sending second output data on the I/O output channel, or de-energizing the I/O channel.