Two-Dimensional CTLE for Programmable Peaking and DC Gain

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Solution Overview

Problem

Designing an efficient continuous-time linear equalizer (CTLE) with programmable DC gain and peaking gain is challenging due to the need to consider various factors, including parasitic components and unpredictable tuning, which affects the equalizer's performance in high-frequency applications.

Innovation Solution

A two-dimensional CTLE with parallel signal paths having different effective gm transfer functions, allowing for programmable peaking gain through weighted summation, and a differential linear equalizer design with specific transistor and impedance element configurations to control the transfer function and maintain zero frequency stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a CTLE is designed with programmable DC gain and peaking gain to improve equalization performance, then the equalization capability is improved, but the device complexity increases due to multiple gain control mechanisms

Engineering Contradiction:
Improveequalization performanceVSAvoidgain control structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The equalizer is divided into multiple parallel signal paths (first and second paths) with different effective gm transfer functions. Each path has its own gain control transistors and impedance elements, allowing independent control of DC gain and peaking gain. This segmentation enables programmable gain control while maintaining manageable complexity through modular architecture.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from traditional single-path CTLE design to a two-dimensional architecture with parallel signal paths. By adding the dimension of parallel paths with different transfer functions, the system achieves independent control of multiple gain parameters (DC gain and peaking gain) simultaneously, resolving the contradiction between performance and complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Device complexity

If traditional CTLE designs are used, then the structure is simple, but parasitic components and unpredictable tuning affect performance at high frequencies

Engineering Contradiction:
ImprovestructureVSAvoidhigh-frequency performance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

Different signal paths are assigned different effective gm transfer functions tailored to specific frequency ranges. The first path handles DC and low-frequency components while the second path handles high-frequency components. This local optimization of transfer functions for different frequency bands improves high-frequency performance without requiring complete redesign of the entire structure.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

Gain control transistors are introduced as intermediary elements between the input signals and the output. These transistors provide controlled attenuation or amplification of specific frequency components, allowing precise tuning of the transfer function to compensate for parasitic effects and channel loss at high frequencies while maintaining overall structural simplicity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11296667B1Two-dimensional continuous-time linear equalizer for high-speed applications
Publication Date: 2022.04.05 NXP BV
  • US11296667B1 patent drawing
  • US11296667B1 patent drawing
  • US11296667B1 patent drawing

AI summary

Embodiments of a linear equalizer are disclosed. In an embodiment, a linear equalizer includes a plurality of input transistors, a plurality of gain control transistors and first and second impedance elements. The plurality of input transistors is connected to input terminals of the linear equalizer to receive input signals. The plurality of gain control transistors is connected between a supply voltage and the plurality of input transistors. The plurality of gain control transistors is also connected to gain control terminals to receive gain control signals. At least some of the gain control transistors are connected to output terminals of the linear equalizer to transmit output signals. The first and second impedance elements are connected between at least some of the input transistors and at least one fixed voltage. A peaking gain of the linear equalizer is defined by gain control signals applied to the gain control terminals.