Two-Layer Cathode Structure for Fast-Switching Power Semiconductors
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Solution Overview
Problem
Existing power semiconductor devices face challenges in controlling the tradeoff characteristics between ON voltage and switching loss, particularly in achieving high-speed operation without relying on carrier lifetime control techniques.
Innovation Solution
A power semiconductor device is designed with a semiconductor substrate having a drift layer, a buffer layer, and a two-layered cathode structure, where the first cathode layer has a higher impurity concentration and crystal defect density, and the second cathode layer has a lower impurity concentration, both contacting the buffer layer, with the cathode layers absent in the intermediate and terminal regions, allowing for improved breakdown tolerance and reduced switching loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If carrier lifetime control technique is used, then tradeoff characteristics between ON voltage and switching loss can be controlled, but the device becomes dependent on charged particles or heavy metals which are inefficient and complex
Solution Approach 1:
The patent extracts and eliminates the dependence on carrier lifetime control techniques (charged particles or heavy metals) by using a purely structural solution. The two-layered cathode layer structure with different impurity concentrations achieves the same performance improvement without requiring external control methods, thereby simplifying the device and removing harmful dependencies.
Solution Approach 2:
The patent changes the structural parameters of the cathode layer by introducing a two-layered configuration with different impurity concentrations (first cathode layer with higher concentration contacting the metal layer, second cathode layer with lower concentration contacting the buffer layer). This parameter change enables control of tradeoff characteristics between ON voltage and switching loss without relying on carrier lifetime control techniques.
2Reliability
If n+ cathode structure is provided in terminal region, then breakdown tolerance is improved, but rising voltage of output characteristics increases
Solution Approach 1:
The patent applies local quality by providing the two-layered cathode structure selectively in the active cell region while omitting it in the intermediate and terminal regions. The first cathode layer with higher impurity concentration is placed where it is most needed for breakdown tolerance, while the second cathode layer with lower impurity concentration is placed to minimize impact on output characteristics, achieving localized optimization.
Solution Approach 2:
The cathode layer is segmented into two distinct layers with different impurity concentrations and crystal defect densities. The first cathode layer contacts the metal layer and provides high breakdown tolerance, while the second cathode layer contacts the buffer layer and moderates the impact on output characteristics, allowing independent optimization of each function.
3Loss of energy
If lifetime killer is introduced, then switching loss is reduced, but ON voltage at rated current density increases
Solution Approach 1:
The patent changes the impurity concentration parameters of the cathode layer by creating a two-layered structure where the first cathode layer has higher impurity concentration (for breakdown tolerance) and the second cathode layer has lower impurity concentration (for reduced switching loss). This parameter optimization achieves reduced switching loss without the need for lifetime killers that would increase ON voltage.
Data Source
AI summary
In a power semiconductor device, the present disclosure is intended to control tradeoff characteristics while realizing operation in a high-speed side range of the tradeoff characteristics without depending on a carrier lifetime control technique. An n+ cathode layer includes a first n+ cathode layer contacting a second metal layer, and a second n+ cathode layer provided between the first n+ cathode layer and an n buffer layer while contacting the first n+ cathode layer and the n buffer layer. Crystal defect density in the first n+ cathode layer is higher than crystal defect density in the second n+ cathode layer. The n+ cathode layer is absent in an intermediate region and a terminal region.