Two-Layer ECC Circuit for Quad-Bit Memory Error Correction
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Solution Overview
Problem
Memory devices often experience higher failure rates than can be corrected with two or three bit error correction, leading to discarded devices and reduced yields during manufacturing.
Innovation Solution
Implementing a two-layer quad bit error correction system using Hamming and Golay codes, where data is encoded with Hamming and Golay code bits before storage, and decoded using Golay and Hamming correction vectors to correct errors, allowing for up to quad bit error correction while maintaining compatibility with industry standard interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two bit error correction is implemented, then device complexity is reduced, but reliability deteriorates because higher failure rates cannot be corrected
Solution Approach 1:
The error correction system is divided into two distinct layers: a first layer using Hamming codes for single bit error correction, and a second layer using Golay codes for additional error correction. This segmentation allows the system to handle higher failure rates by distributing correction capabilities across multiple specialized components rather than using a single complex correction mechanism.
Solution Approach 2:
The patent combines two different error correction coding schemes (Hamming and Golay codes) into a hybrid correction system. This composite approach leverages the strengths of both coding methods to achieve quad bit error correction capability, effectively creating a more robust correction system that can handle higher failure rates than either code could achieve alone.
2Reliability
If quad bit error correction is implemented, then reliability is improved, but device complexity increases
Solution Approach 1:
The correction process is segmented into sequential stages: first layer correction using Hamming codes, followed by second layer correction using Golay codes. This segmentation breaks down the complex quad bit correction task into manageable stages, where each layer handles specific error patterns, reducing the overall system complexity while maintaining high reliability.
Solution Approach 2:
The patent introduces a dimensional aspect to error correction by implementing a two-layer hierarchical structure. Instead of a single flat correction layer, the system adds a vertical dimension with multiple correction layers, allowing errors to be addressed at different levels of correction intensity, thereby managing complexity through structured organization.
3Reliability
If more error correction bits are added, then reliability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The correction bits are segmented and distributed across two layers with different coding schemes. The first layer uses Hamming codes with specific parity bit arrangements, while the second layer uses Golay codes with different bit allocation. This segmentation allows each layer to operate with its own precision requirements rather than demanding uniform high precision across all correction bits.
Solution Approach 2:
The patent changes the parameters of error correction by switching between different coding schemes (Hamming and Golay) with different characteristics. Each coding scheme has different bit requirements, parity structures, and correction capabilities, allowing the system to adapt precision requirements to the specific error patterns encountered at each correction layer.
Data Source
AI summary
A memory device includes one or more memory arrays and a quad bit error correction circuit. The quad bit error correction circuit may include a first layer error correction circuit and a second layer error correction circuit. The first layer error correction circuit may be configured to generate a Hamming correction bit vector, and the second layer error correction circuit may be configured to generate a Golay correction bit vector. The Hamming correction bit vector and the Golay correction bit vector may be used to identify up to four correctable bit errors in data to be stored in the one more memory arrays.