Two-Layer Memory Coding for Low-Parity Concurrent Writes
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Solution Overview
Problem
Memory sub-systems face media access collisions and increased buffer lifetime due to fixed media layouts, leading to inefficiencies in data storage and retrieval, particularly when multiple write streams are executed concurrently.
Innovation Solution
Implementing dynamic data placement that postpones media layout determination until write commands can be executed without collisions, mapping logical addresses to available integrated circuit dies for concurrent operations, and using a two-layer code with low parity cost for error correction across multiple planes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a fixed media layout is used for data storage, then the media layout determination is simple and fast, but media access collisions occur and buffer lifetime increases
Solution Approach 1:
The patent implements dynamic media layout determination that adapts to the current state of integrated circuit dies. Instead of using a fixed layout, the system dynamically selects and updates media layouts based on which dies are available and busy, allowing write commands to be executed without collisions by mapping logical addresses to available physical locations in real-time.
2Productivity
If multiple write streams are executed concurrently, then the data throughput increases, but media access collisions increase
Solution Approach 1:
The patent introduces a dynamic data placer as an intermediary component that manages multiple write streams. This data placer receives write commands, determines current die availability, and dynamically maps logical addresses to physical locations across multiple integrated circuit dies, thereby coordinating concurrent write operations to avoid collisions while maintaining high throughput.
3Reliability
If dynamic data placement is implemented, then media access collisions are eliminated, but the complexity of media layout determination increases
Solution Approach 1:
The patent maintains a data structure that pre-tracks the busy status of integrated circuit dies. This preliminary tracking of die availability allows the dynamic data placer to quickly determine suitable target locations for write commands without complex real-time analysis, reducing the computational complexity while still achieving collision-free execution.
Data Source
AI summary
A memory sub-system configured to encode data using an error correcting code and an erasure code for storing data into memory cells and to decode data retrieved from the memory cells. For example, the data units of a predetermined size are separately encoded using the error correcting code (e.g., a low-density parity-check (LDPC) code) to generate parity data of a first layer. Symbols within the data units are cross encoded using the erasure code. Parity symbols of a second layer are calculated according to the erasure code. A collection of parity symbols having a total size equal to the predetermined size can be further encoded using the error correcting code to generate parity data for the parity symbols.