Two-Layer Motherboard Tester for Integrated DRAM Burn-In

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Solution Overview

Problem

Existing DRAM component testing processes are costly, complicated, and risk damaging the components due to the need for multiple test systems and handling, which involves expensive equipment and multiple handling steps, leading to contact damage.

Innovation Solution

A tester board system with a frame and multiple motherboards, where each motherboard has CPUs on one side and memory channels on the other, aligned horizontally, with a gap and insulation to protect CPUs from temperature variations, allowing for integrated testing without the need for large BI systems.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple separate test systems are used for BI, weak cell, and speed testing, then comprehensive testing coverage is achieved, but handling damage to contacts increases and testing complexity increases

Engineering Contradiction:

Improvetesting coverageVSAvoidhandling damage

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent combines multiple separate test systems (BI tester, weak cell tester, speed tester) into a single integrated tester board that can perform all three testing functions. The tester board includes a frame with multiple motherboards, each having CPUs and memory channels that can conduct burn-in testing, weak cell testing, and speed testing simultaneously, eliminating the need to physically handle and transfer components between different test systems.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The tester board is designed as a universal testing platform that can perform multiple types of memory testing functions. Each motherboard contains CPUs and memory channels capable of executing different test modes (BI, weak cell, speed testing) on the same physical hardware, making the system multi-functional and eliminating the need for separate specialized test equipment.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If multiple separate test systems are used for BI, weak cell, and speed testing, then comprehensive testing coverage is achieved, but device complexity and cost increase

Engineering Contradiction:

Improvetesting coverageVSAvoidsystem complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

Inventive Principle:

Principle #5Merging (Combining)

3Temperature

If components are tested at different temperatures requiring removal between tests, then temperature-specific testing requirements are met, but handling damage increases

Engineering Contradiction:

Improvetesting temperatureVSAvoidhandling damage

Core Design Contradiction:

TemperatureVSObject-affected harmful factors

Solution Approach 1:

Inventive Principle:

Principle #6Universality (Multi-functionality)

4Temperature

If CPUs are exposed to temperature variations during testing, then temperature testing is enabled, but CPU reliability decreases

Engineering Contradiction:

Improvetesting temperatureVSAvoidCPU reliability

Core Design Contradiction:

TemperatureVSReliability

Solution Approach 1:

The tester board structure segments the testing area from the CPU area. The frame design allows memory modules to be tested at elevated temperatures while the CPUs remain in a separate, temperature-controlled environment. This spatial segmentation enables temperature testing of memory components without exposing the CPUs to harmful thermal conditions.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The motherboard acts as an intermediary between the temperature-controlled testing environment and the CPU. The board allows memory modules to be subjected to temperature variations while the CPU remains protected, with the motherboard serving as the interface that enables temperature testing without directly exposing the CPU to extreme conditions.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS12480985B2Multiple tile two-layered motherboard tester

Publication Date: 2025.11.25 INTELLIGENT MEMORY LTD

AI summary

A tester board system that includes a frame upon which a plurality of motherboard assemblies can be inserted for the purposes of BI and other types of component testing. Each motherboard assembly has memory channels disposed on an upper motherboard that can accommodate a plurality of memory components for testing, and the memory channels are connected to a CPU. The CPU is disposed on a lower motherboard and the memory channels are connected to the CPU via communication connectors that are passed via a connection column between the upper and lower motherboards.