Two-Layer Spacer Protection for Semiconductor Gate Etching
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Solution Overview
Problem
In semiconductor fabrication processes for devices smaller than 0.13 um, the gate dielectric and polysilicon gate structures have low etching resistance to hydrofluoric and phosphoric acid solutions, leading to reduced reliability and performance due to etching during deglazing and mask removal processes.
Innovation Solution
A semiconductor fabricating process using two layers of spacers, where a first spacer of silicon oxide and a second spacer of silicon nitride or silicon carbide are formed on the sidewalls of the gate structure, allowing for controlled etching processes with hydrofluoric and phosphoric acid solutions to protect the gate structure from damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If hydrofluoric acid solution is used to remove impurities during deglazing, then cleaning effectiveness is improved, but gate dielectric layer is etched and damaged
Solution Approach 1:
The patent introduces an intermediary protective layer (such as spin-on-glass or other dielectric materials) between the hydrofluoric acid solution and the gate dielectric layer. This intermediary layer allows the HF solution to effectively clean impurities while preventing direct contact with and etching of the gate dielectric layer, thus resolving the contradiction between cleaning effectiveness and layer integrity.
2Ease of manufacture
If hot phosphoric acid solution is used to remove gate mask layer, then mask removal effectiveness is improved, but gate line width is reduced due to etching
Solution Approach 1:
The patent introduces a protective layer as an intermediary between the hot phosphoric acid solution and the gate structure. This protective layer enables effective removal of the gate mask layer while preventing the phosphoric acid from etching the gate and altering its line width, thus maintaining manufacturing precision while achieving effective mask removal.
3Reliability
If conventional single-layer spacer protection is used, then some protection is provided, but insufficient protection against both hydrofluoric and phosphoric acid etching is achieved
Solution Approach 1:
The patent divides the protective spacer structure into multiple segments or layers (such as a first protective layer and a second protective layer with different materials and properties). Each layer is optimized to resist specific acids, providing comprehensive protection against both hydrofluoric and phosphoric acid etching, thus improving reliability while managing complexity through functional segmentation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of two-layer spacers effectively prevents etching of the gate dielectric and polysilicon gate structures, enhancing the reliability and performance of the semiconductor device by maintaining the integrity of the gate structure during acid-based etching processes.
Implementation Method 1
the oxide layer is, for example, formed by performing a rapid thermal oxidation process
Implementation Method 2
a first etching process is performed to remove the oxide layer on the surface of the mask layer... a solution used in the first etching process comprises a hydrofluoric acid solution
Implementation Method 3
a second etching process is performed to simultaneously remove the mask layer and the second spacer... a solution used in the second etching process comprises a phosphoric acid solution
Data Source
AI summary
A semiconductor fabricating process is provided. First, a substrate is provided. The substrate has thereon a stacked structure and a mask layer disposed on the stacked structure. Thereafter, an oxide layer is formed on a surface of the mask layer and a surface of at least a portion of the stacked structure. Afterwards, a first spacer is formed on a sidewall of the stacked structure. Then, a second spacer is formed on a sidewall of the first spacer. Further, a first etching process is performed to remove the oxide layer on the surface of the mask layer. Thereafter, a second etching process is performed to simultaneously remove the mask layer and the second spacer.