Two-Layer STI Isolation for Uniform FinFET Fin Heights
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Solution Overview
Problem
In the manufacturing of FinFETs, the formation of Shallow Trench Isolation (STI) regions faces challenges in achieving uniformity of fin heights due to differences in etching rates of dielectric layers, leading to pattern loading effects and non-uniformity in integrated circuits.
Innovation Solution
The method involves forming STI regions through two distinct dielectric layers with different properties, where a first dielectric layer is treated with UV in an oxygen-containing environment and a second layer with thermal treatment, followed by annealing, to create layers with distinct reflective indices, thereby controlling etching rates and improving fin height uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single dielectric layer is used for STI regions, then the manufacturing process is simpler, but the fin height uniformity deteriorates due to pattern loading effects during etching
Solution Approach 1:
The dielectric layer is segmented into two distinct layers: a first dielectric layer (e.g., silicon nitride) and a second dielectric layer (e.g., silicon oxide). This segmentation allows each layer to have different etching rates, enabling the upper portion and lower portion of trenches to be filled with materials optimized for different etching conditions, thereby achieving uniform fin heights while maintaining process feasibility
Solution Approach 2:
Different dielectric materials are assigned to different spatial locations within the STI structure. The first dielectric layer is positioned in the lower portion of trenches where different etching characteristics are needed compared to the upper portion filled with the second dielectric layer. This local differentiation of material properties enables precise control over etching rates in different regions, resolving the uniformity issue
2Manufacturing precision
If different dielectric layers with different etching rates are used, then fin height uniformity is improved, but the device complexity increases
Solution Approach 1:
The invention changes the material composition parameter of the dielectric layers, using two different dielectric materials with distinctly different etching rates (e.g., silicon nitride with slower etching rate and silicon oxide with faster etching rate). This parameter change enables differential etching behavior that compensates for pattern loading effects, achieving uniform fin heights without requiring complex additional processing steps
3Manufacturing precision
If UV treatment is applied to the first dielectric layer, then the etching rate control is improved, but the process time increases
Solution Approach 1:
The invention replaces traditional thermal or chemical post-treatment methods with UV light treatment for the first dielectric layer. This substitution enables more precise and uniform modification of the dielectric layer properties, improving etching rate control and fin height uniformity while potentially reducing overall process time compared to extended thermal annealing or chemical treatments
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the uniformity of fin heights across the semiconductor die/wafer by managing the etching rates of dielectric layers, reducing pattern loading effects and improving the overall performance of integrated circuits.
Implementation Method 1
a first dielectric layer is treated with UV in an oxygen-containing environment
Implementation Method 2
a second layer with thermal treatment
Implementation Method 3
followed by annealing
Data Source
AI summary
A method includes etching a semiconductor substrate to form trenches extending into the semiconductor substrate, and depositing a first dielectric layer into the trenches. The first dielectric layer fills lower portions of the trenches. A Ultra-Violet (UV) treatment is performed on the first dielectric layer in an oxygen-containing process gas. The method further includes depositing a second dielectric layer into the trenches. The second dielectric layer fills upper portions of the trenches. A thermal treatment is performed on the second dielectric layer in an additional oxygen-containing process gas. After the thermal treatment, an anneal is performed on the first dielectric layer and the second dielectric layer.