Two-Level Cache Tagging for Miss Handling and Stall Reduction

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Solution Overview

Problem

Cache operations in data processing systems face inefficiencies when fetching data from one cache requires data from another cache, leading to potential cache misses and processing stalls, particularly in graphics processing systems where texture sample data depends on additional memory addresses.

Innovation Solution

A two-step process is implemented where a first cache allocates an entry and tags it with information from a second cache to facilitate data fetching, allowing the first cache to store either an entry identifier or a memory address, reducing the need for simultaneous storage of both types of information and minimizing performance impact.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data fetching from first cache requires data from second cache, then data dependency is resolved, but processing stalls occur due to cache misses

Engineering Contradiction:
Improvedata fetching reliabilityVSAvoidprocessing stall time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by performing a look-up in the second cache before attempting to fetch data from the first cache. This advance check determines whether the required data is available in the second cache, allowing the system to prepare appropriately before the actual data fetch operation, thereby reducing processing stalls.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses the second cache as an intermediary structure to store information about data locations and availability. Before accessing the first cache, the system queries the second cache to obtain necessary information, which mediates the data fetching process and reduces direct dependency conflicts between caches.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of information

If both entry identifier and memory address are stored in cache tag, then complete information is available, but storage complexity and cost increase

Engineering Contradiction:
Improvecache information completenessVSAvoidcache storage structure
Core Design Contradiction:
Loss of informationVSDevice complexity

Solution Approach 1:

The patent segments the cache tag structure into different functional parts: one portion stores entry identifiers for indexing into the second cache, while another portion stores memory addresses. This segmentation allows the system to store only the necessary information in each location, reducing overall storage complexity while maintaining information completeness.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from storing all information in a single cache dimension to using a two-dimensional approach: the first cache stores data with segmented tag information, while the second cache stores additional information in a separate dimension. This dimensional separation reduces the storage burden on any single cache structure.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12517835B2Cache operation in data processing systems
Publication Date: 2026.01.06 ARM LTD
  • US12517835B2 patent drawing
  • US12517835B2 patent drawing
  • US12517835B2 patent drawing

AI summary

In a data processing system comprising a first cache operable to store data for use when performing a data processing operation, and a second cache operable to store data required for fetching data into the first cache from memory, when it is determined that there is no entry for data for a data processing operation in the first cache, an entry in the first cache is allocated for the required data, and information that indicates an entry in the second cache for data required for fetching the required data is stored in the tag portion of the allocated entry. Then, once a request has been sent to a memory system for the required data, the information in the tag portion for the allocated entry in the first cache that indicates an entry in the second cache is replaced with information indicative of an address for the data required for fetching the required data.