Two-Level ECC Check-Bit Sharing for Low-Latency Memory Protection
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Solution Overview
Problem
Existing memory systems face challenges in effectively protecting data integrity due to bit corruption caused by environmental and internal factors, requiring efficient error correction mechanisms that balance error detection and correction capabilities with minimal overhead and latency.
Innovation Solution
A two-level error correction code (ECC) system is implemented, comprising a first level ECC for error detection in smaller words and a second level ECC for error correction in larger words, with sharing of check bits between the two levels to reduce overhead and latency, using Hamming codes and XOR trees for error detection and correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional single-level ECC is used for error correction in memory systems, then error detection and correction capability is provided, but overhead and latency increase
Solution Approach 1:
The ECC system is divided into two hierarchical levels: first-level ECC circuits operate on smaller data units (e.g., 64-bit words) while second-level ECC circuits operate on larger data units (e.g., 512-bit words). This segmentation allows parallel processing at multiple granularities, reducing overall latency while maintaining comprehensive error protection capability.
Solution Approach 2:
The patent introduces a hierarchical dimension to the ECC architecture, organizing error correction operations across multiple levels rather than a single flat level. This dimensional organization enables simultaneous operation of multiple ECC circuits at different levels, improving throughput and reducing latency.
2Reliability
If more check bits are added to improve error correction capability, then reliability increases, but overhead increases
Solution Approach 1:
The patent merges the functionality of multiple ECC circuits into a hierarchical structure where second-level ECC circuits handle errors that escape first-level detection. This consolidation reduces the total number of check bits required compared to using multiple independent full-capability ECC circuits, as the hierarchical arrangement allows shared error correction resources.
Solution Approach 2:
The second-level ECC circuits serve multiple functions: they correct errors that were not detected by first-level ECC, and they provide protection for the first-level check bits themselves. This multi-functionality reduces the overall overhead by eliminating redundant error protection mechanisms.
3Reliability
If multiple independent ECC circuits are used for comprehensive error protection, then error correction capability improves, but device complexity increases
Solution Approach 1:
The ECC architecture implements a nested structure where first-level ECC circuits are embedded within a second-level ECC framework. The first-level circuits handle routine error correction, while second-level circuits provide overarching protection. This nesting reduces complexity by organizing multiple ECC functions in a hierarchical manner rather than requiring fully independent parallel circuits.
Solution Approach 2:
The system dynamically selects which ECC level to activate based on error detection results. First-level ECC is activated for standard operations, while second-level ECC is activated when first-level detection indicates potential errors. This dynamic activation reduces the effective complexity by not requiring all ECC circuits to operate simultaneously at full capacity.
Data Source
AI summary
A memory device includes: a memory device configured to store data bits to be written to the memory device; and a memory controller. The memory controller includes: a first level error correction code (ECC) circuit coupled to the memory device, wherein the first level ECC circuit is configured to generate a first plurality of first level check bits corresponding to the data bits based on a first error detection scheme; and a second level ECC circuit coupled to the memory device, wherein the second level ECC circuit is configured to generate a second plurality of second level check bits corresponding to both the data bits and the first plurality of first level check bits based on a first error correction scheme.