Two-Level ECC Check-Bit Sharing for Low-Overhead Memory Protection
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Solution Overview
Problem
Existing memory systems face challenges in protecting data integrity due to bit corruption caused by environmental and internal factors, such as particle strikes, which can lead to system failure and data loss, and current error correction codes (ECC) require additional memory space for check bits, increasing overhead and latency.
Innovation Solution
A two-level ECC memory controller is implemented, which includes a first level ECC for error detection in smaller words and a second level ECC for error correction in larger words, with shared check bits to minimize overhead and latency, and a method for sharing check bits between the two levels to further reduce resource requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ECC is implemented to protect data integrity, then error detection and correction capability is improved, but memory overhead and latency increase
Solution Approach 1:
The patent divides the ECC protection into two hierarchical levels: first-level ECC operates on smaller data units (e.g., 64-bit words) while second-level ECC operates on larger aggregated units (e.g., 512-bit cache lines). This segmentation allows each level to use optimized check bit schemes, reducing total overhead compared to applying single-level ECC across all data sizes.
Solution Approach 2:
The patent implements nested ECC where first-level check bits are generated for small data units, then these check bits along with the original data are further processed by second-level ECC to generate additional check bits. This nested structure enables efficient error correction at multiple granularities while minimizing redundant check bits through the sharing mechanism.
2Reliability
If check bits are added for error correction, then error detection and correction capability is improved, but latency increases
Solution Approach 1:
The patent performs first-level ECC check bit generation during the write operation before data is stored in memory. This preliminary action ensures that when data is read, the first-level check bits are already available, and only the second-level check bit generation and verification are needed, reducing read latency while maintaining comprehensive error correction capability.
Solution Approach 2:
By segmenting ECC operations into two levels with different scopes, the patent enables parallel processing where first-level ECC operates on individual small words while second-level ECC operates on aggregated blocks. This segmentation allows the system to benefit from faster first-level verification for frequently accessed small data units while maintaining robust second-level protection.
3Reliability
If more check bits are used for comprehensive error protection, then error detection and correction capability is improved, but resource requirements increase
Solution Approach 1:
The patent makes check bits serve multiple functions across different ECC levels. First-level check bits are used both for protecting individual small data units and as input to the second-level ECC process. This multi-functionality reduces the total number of check bits required compared to having separate, independent ECC schemes for each data unit.
Solution Approach 2:
The patent merges the first-level and second-level ECC operations by having the second-level check bit generation process take both the original data and first-level check bits as inputs. This merging eliminates redundancy where the same data bits would otherwise be processed independently at each level, reducing the total check bit overhead while maintaining comprehensive error protection.
Data Source
AI summary
A memory device includes: a memory device configured to store data bits to be written to the memory device; and a memory controller. The memory controller includes: a first level error correction code (ECC) circuit coupled to the memory device, wherein the first level ECC circuit is configured to generate a first plurality of first level check bits corresponding to the data bits based on a first error detection scheme; and a second level ECC circuit coupled to the memory device, wherein the second level ECC circuit is configured to generate a second plurality of second level check bits corresponding to both the data bits and the first plurality of first level check bits based on a first error correction scheme.