Two-Level Field Plate Semiconductor Device for Breakdown Voltage

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional LDMOS devices have insufficient depletion of the drift region due to a single-level field plate, limiting their breakdown voltage and electric field optimization at the gate polycrystalline boundary.

Innovation Solution

A method of manufacturing a semiconductor device involving the formation of a first field plate self-aligned with a gate polycrystalline and a second field plate on a second field oxide, enhancing the depletion of the drift region and improving the electric field at the gate boundary through a two-level field plate configuration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single-level field plate is formed in the drift region, then the structure is simple and manufacturing is easier, but the depletion of the drift region is insufficient and breakdown voltage is limited

Engineering Contradiction:
Improvefield plate structureVSAvoidbreakdown voltage
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The field plate structure is segmented into two levels: a first field plate formed at a first potential and a second field plate formed at a second potential. This segmentation allows independent optimization of electric field control at different regions, enhancing drift region depletion and increasing breakdown voltage while maintaining manufacturing feasibility through sequential formation processes

Inventive Principle:
Principle #1Segmentation

2Device complexity

If a single-level field plate is used, then the manufacturing process is simpler, but the electric field optimization at the gate polycrystalline boundary is limited

Engineering Contradiction:
Improvefield plate configurationVSAvoidelectric field optimization
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

Different field plates are applied to different regions with different electrical characteristics. The first field plate optimizes the electric field at the gate polycrystalline boundary region, while the second field plate enhances depletion in the drift region. This local quality approach allows precise electric field control in each critical region, improving manufacturing precision for high-voltage device characteristics

Inventive Principle:
Principle #3Local quality

3Device complexity

If only one field plate level is provided, then the process is simpler, but the depletion of the drift region remains insufficient

Engineering Contradiction:
Improvefield plate levelsVSAvoiddrift region depletion
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The field plate structure is extended from a single-level (one-dimensional) configuration to a two-level (multi-dimensional) configuration. The first field plate is formed at a first height level and the second field plate is formed at a second height level, creating a multi-dimensional electric field control structure that enhances drift region depletion effectiveness without excessive process complexity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The two-level field plate configuration increases the breakdown voltage of the semiconductor device by improving the depletion of the drift region and optimizing the electric field, addressing the limitations of conventional technologies.

Implementation Method 1

forming a drift region in the semiconductor substrate by ion implantation using a drift region masking layer as a mask

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS11462628B2Semiconductor device, and manufacturing method thereof
Publication Date: 2022.10.04 CSMC TECH FAB2 CO LTD
  • US11462628B2 patent drawing
  • US11462628B2 patent drawing
  • US11462628B2 patent drawing

AI summary

A semiconductor device, and a manufacturing method thereof. The method includes: providing a semiconductor substrate provided with a body region, a gate dielectric layer, and a field oxide layer, formed on the semiconductor substrate; forming a gate polycrystalline, the gate polycrystalline covering the gate dielectric layer and the field oxide layer and exposing at least one portion of the field oxide layer; forming a drift region in the semiconductor substrate by ion implantation using a drift region masking layer as a mask, removing the exposed portion of the field oxide layer by further using the drift region masking layer as the mask to form a first field oxide self-aligned with the gate polycrystalline; forming a source region in the body region, and forming a drain region in the drift region; forming a second field oxide on the semiconductor substrate; and forming a second field plate on the second field oxide.