Two-Level Interrupt Service Routine for Processor Delay Reduction
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Solution Overview
Problem
Conventional interrupt handling in processors experiences delays due to the need to transfer ISR address information via a system bus, leading to inefficiencies and increased error likelihood, as each Second-Level Interrupt Handler (SLIH) routine contains duplicative common first-level interrupt handling code.
Innovation Solution
A processor with an interrupt handler that stores an interrupt identifier and executes a common Interrupt Service Routine (ISR) before initiating a device-specific SLIH routine, allowing for efficient interrupt servicing by recognizing interrupt requests, saving identifiers, and executing FLIH routines before SLIH routines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If ISR address information is transferred via system bus, then the system bus can be used for general purposes, but interrupt service delay increases
Solution Approach 1:
The patent pre-loads ISR address information into dedicated buffer registers within the processor before interrupt requests occur. This preliminary action allows the processor to immediately access ISR addresses without waiting for system bus transfers when interrupts are asserted, thereby reducing interrupt service delay while maintaining system bus availability for other operations.
2Ease of operation
If SLIH routines contain duplicative FLIH code, then each routine can operate independently, but code complexity and error likelihood increase
Solution Approach 1:
The patent segments interrupt handling functionality into two distinct parts: a common First-Level Interrupt Handler (FLIH) routine containing shared initialization and processing code, and device-specific Second-Level Interrupt Handler (SLIH) routines that only contain device-specific logic. This segmentation eliminates code duplication while maintaining independent operation of each SLIH routine through controlled entry points and parameter passing mechanisms.
Solution Approach 2:
The patent merges common interrupt handling functionality into a single shared FLIH routine that is invoked by all interrupt sources. This consolidation eliminates redundant code across multiple SLIH routines while preserving their independence through a standardized interface. The FLIH routine handles common tasks such as saving processor state, validating interrupt requests, and coordinating with the interrupt controller, thereby reducing overall code complexity and error likelihood.
3Speed
If processor immediately initiates SLIH routine without FLIH, then interrupt response time is reduced, but code portability decreases
Solution Approach 1:
The patent performs preliminary actions within the FLIH routine that are essential for proper interrupt handling, such as saving processor context, configuring interrupt masks, and initializing common data structures. These preliminary actions are executed once for all interrupts, allowing subsequent SLIH routines to focus solely on device-specific processing. This approach maintains fast response times while improving code portability through standardized initialization sequences that can be adapted to different architectures.
Data Source
AI summary
A processor provides two-level interrupt servicing. In one embodiment, the processor comprises a storage device and an interrupt handler. The storage device is configured to store an interrupt identifier corresponding to an interrupt request. The interrupt handler is configured to recognize the interrupt request, initiate a common interrupt service routine responsive to recognizing the interrupt request and subsequently initiate an interrupt service routine corresponding to the stored interrupt identifier.