Two-Level Linked List Descriptor for DMA Efficiency
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Solution Overview
Problem
Current memory systems using linked list descriptors face limitations such as the need for separate descriptors for different data sizes and lack of hardware-assisted rewind and retry capabilities, leading to inefficiencies in DMA operations and increased CPU intervention.
Innovation Solution
Implementing a two-level linked list descriptor mechanism with second-level descriptors that allow data size adjustments and include tracking information for rewind and retry operations, enabling sharing of first-level descriptors between DMA modules and reducing CPU intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate descriptors are used for different data sizes, then data transfer accuracy is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal descriptor structure that can handle multiple data sizes through a second-level descriptor mechanism. The first-level descriptors serve multiple purposes by linking to second-level descriptors that contain data size information, allowing the same first-level descriptor format to work with variable data lengths without requiring separate descriptor structures for each data size.
Solution Approach 2:
The patent employs a nested descriptor structure where second-level descriptors are embedded within the linked list of first-level descriptors. Each first-level descriptor contains a pointer to a second-level descriptor, creating a hierarchical nesting that allows data size information to be stored within the existing descriptor framework rather than requiring separate structures.
2Reliability
If hardware-assisted rewind and retry capabilities are added, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements preliminary action by pre-storing the address of the first descriptor in the second-level descriptor structure before DMA operations begin. This pre-stored address enables the DMA controller to quickly rewind to the start of the descriptor chain without requiring complex real-time calculations, simplifying the hardware rewind mechanism while maintaining reliability.
Solution Approach 2:
The second-level descriptor acts as an intermediary structure that mediates between the first-level descriptors and the DMA controller's error handling requirements. By placing data size information and rewind addresses in the second-level descriptor, the patent provides the DMA controller with the necessary information for reliable error recovery without requiring complex hardware logic.
3Productivity
If CPU intervention is reduced, then productivity is improved, but ease of operation worsens
Solution Approach 1:
The patent implements self-service by enabling the DMA controller to autonomously perform rewind and retry operations using information stored in the second-level descriptors. The DMA controller reads the pre-stored first descriptor address from the second-level descriptor and automatically rewinds and retries without requiring CPU or firmware intervention, thereby improving productivity while maintaining ease of operation through hardware automation.
Solution Approach 2:
The patent employs feedback mechanisms where the DMA controller monitors DMA operation status and automatically triggers rewind and retry operations based on error conditions detected during transfer. This feedback loop, controlled by hardware rather than firmware, allows the system to maintain ease of operation while significantly improving productivity by eliminating CPU intervention in routine error handling.
Data Source
AI summary
In an embodiment of the invention, a method for to use a two level linked list descriptor mechanism to pass information among flash, memory, and IO controller modules is presented. The method includes creating a first level data structure for one or more first level descriptors; creating a second level data structure for one or more second level descriptors, each second level descriptor having a pointer to tracking information that includes start information, running information, and rewind information for a data DMA; using the one or more second level descriptors, the one or more first level descriptors, and the tracking information for a data DMA; updating the tracking information during the data DMA; and updating the tracking information at the end of the data DMA.