Two-Level Main Memory System for Capacity Expansion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current main memory systems, relying on dynamic random access memory (DRAM) modules, face limitations in memory density and cost, requiring multiple modules to increase capacity, which adversely affects the form factor, especially in mobile devices.
Innovation Solution
A two-level main memory system comprising a smaller, faster near memory (DRAM) and a larger, slower far memory (volatile or nonvolatile storage) that is transparent to the operating system, with a 2LM engine managing data transfer and wear-leveling, enabling efficient capacity expansion without increasing system volume.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple DIMM modules are used to increase main memory capacity, then memory capacity is improved, but system volume and cost increase
Solution Approach 1:
The memory system is segmented into two distinct levels: a first level of volatile memory (DRAM) for fast access and a second level of non-volatile memory (flash storage) for capacity. This segmentation allows the system to achieve high capacity without proportionally increasing volume, as the non-volatile memory provides dense storage in a compact form factor.
Solution Approach 2:
The patent introduces a hierarchical memory architecture that adds a temporal dimension to memory access. Instead of merely increasing spatial capacity with more DIMM modules, the system adds a second storage dimension (non-volatile memory) that can be accessed sequentially, effectively decoupling capacity expansion from volume increase.
2Quantity of substance
If multiple DIMM modules are used to increase main memory capacity, then memory capacity is improved, but cost increases
Solution Approach 1:
Different memory technologies are assigned to different functional zones: volatile memory (DRAM) is used locally where speed is critical for active data, while non-volatile memory (flash storage) is used where capacity and cost-effectiveness are priorities. This local quality differentiation optimizes the cost-performance ratio by using cheaper non-volatile memory for bulk storage.
Solution Approach 2:
The system employs non-volatile memory (flash storage) as a cost-effective alternative to expensive volatile memory for bulk capacity requirements. While non-volatile memory has slower access speeds, it provides economical capacity expansion, similar to using disposable storage media for archival purposes.
3Speed
If DRAM is used for main memory, then access speed is improved, but memory density and capacity efficiency deteriorate
Solution Approach 1:
The memory subsystem is segmented into performance-critical volatile memory for fast access and capacity-efficient non-volatile memory for dense storage. This segmentation allows the system to achieve both high speed and high density by distributing data across two media with complementary characteristics.
Solution Approach 2:
The system dynamically manages data between volatile and non-volatile memory based on access patterns and capacity requirements. Hot data is kept in fast volatile memory while cold data is stored in dense non-volatile memory, creating a dynamic balance between speed and density that adapts to workload conditions.
Data Source
AI summary
Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory.The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.