Two-Level Memory Bandwidth Scaling via Dynamic Controller
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Solution Overview
Problem
Current computing systems face challenges in managing memory bandwidth efficiently due to limitations in DRAM density and cost, particularly in mobile devices, where increasing main memory size leads to increased volume and form factor issues, and existing two-level memory systems struggle with power consumption and performance when bandwidth exceeds a certain threshold.
Innovation Solution
A two-level memory (2LM) subsystem architecture is implemented, comprising near memory (DRAM) and far memory (volatile or nonvolatile storage), where near memory acts as a high-bandwidth, low-latency cache for far memory, managed by a 2LM controller that dynamically scales near memory size and bandwidth to optimize power consumption and performance by monitoring and adjusting memory requests, bandwidth utilization, and implementing wear-leveling and data compression techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If main memory size is increased using multiple DIMMs, then memory capacity is improved, but system cost and volume increase
Solution Approach 1:
The memory system is segmented into two distinct levels: near memory (DRAM) and far memory (non-volatile storage). This segmentation allows the system to achieve large total capacity through far memory while keeping the near memory portion small, thus avoiding the volume increase that would result from using multiple large DIMMs.
Solution Approach 2:
The patent introduces a new dimension to the memory hierarchy by adding far memory as a second level beyond traditional DRAM. This creates a multi-layered memory architecture that expands capacity in a different dimensional space rather than simply increasing single-level memory size, thereby avoiding form factor constraints.
2Productivity
If near memory size is increased to handle higher bandwidth, then memory bandwidth capacity is improved, but power consumption increases
Solution Approach 1:
The system dynamically adjusts near memory size and bandwidth allocation based on actual workload demands. The 2LM controller monitors memory access patterns and dynamically scales near memory resources, ensuring high bandwidth is provided only when needed while reducing power consumption during low-demand periods.
Solution Approach 2:
The patent changes key parameters including near memory size, bandwidth allocation, and operational states based on monitored workload conditions. By dynamically adjusting these parameters rather than maintaining fixed high-capacity near memory, the system achieves high bandwidth when needed while minimizing power consumption during normal operation.
3Speed
If far memory bandwidth is increased to match near memory bandwidth, then data transfer speed is improved, but power consumption and cost increase
Solution Approach 1:
The system applies local quality by providing high bandwidth only where and when needed. Near memory maintains high bandwidth for critical operations, while far memory bandwidth is dynamically adjusted based on actual access requirements. This localized approach to bandwidth allocation ensures high data transfer speed when needed without the continuous power consumption of uniformly high bandwidth across the entire memory subsystem.
4Quantity of substance
If multiple DIMMs are used to increase memory size, then memory capacity is improved, but system cost increases
Solution Approach 1:
The patent employs a composite memory architecture combining two different memory technologies: DRAM (near memory) and non-volatile storage (far memory). This composite approach leverages the strengths of each technology type, achieving high capacity at lower cost through far memory while using smaller amounts of expensive DRAM only for high-performance requirements.
Data Source
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AI summary
Memory bandwidth management. In a two-level memory (2LM) system far memory bandwidth utilization at least a far memory is monitored and the available far memory bandwidth availability is dynamically modified based on monitored far memory bandwidth utilization. The operational state of at least one processing core is dynamically modified in response to modification of available far memory bandwidth.