Two-Level Memory Flush Architecture for Low-Power DRAM Standby
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Solution Overview
Problem
The high power consumption of DRAM self-refresh in idle modes of electronic systems, particularly in laptops, leads to significant battery drain and challenges in meeting energy regulations, with existing memory management standards like JEDEC not providing effective implementations for power savings.
Innovation Solution
A two-level memory (2LM) hardware architecture that flushes DRAM content to persistent far memory, powers off the DRAM and memory controller, and uses a hardware accelerator to manage memory retention and restoration without OS involvement, enabling faster system resume from a DRAM off state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DRAM memory enters self-refresh mode during standby states, then data is retained in memory, but power consumption increases significantly
Solution Approach 1:
The patent extracts the data retention function from the DRAM self-refresh operation by moving data to non-volatile memory, allowing the DRAM to be powered down completely while data remains preserved in the non-volatile memory layer
Solution Approach 2:
The patent uses volatile DRAM as a temporary, low-power state buffer that can be quickly powered down and restored, accepting that data must be migrated to non-volatile memory for long-term retention without continuous power
2Use of energy by moving object
If DRAM is powered off to reduce power consumption, then battery life is extended, but system resume time increases
Solution Approach 1:
The patent performs preliminary actions by maintaining a hybrid memory architecture where non-volatile memory is pre-configured to hold data, and the system is prepared with migration pathways ready, enabling faster resume compared to cold boot while still allowing DRAM power-off
3Adaptability or versatility
If software-based memory management is used to handle power states, then flexibility is improved, but system complexity increases
Solution Approach 1:
The patent implements self-service by using hardware-managed memory migration and power state transitions, where the memory controller and hardware accelerator automatically handle data movement and power management without requiring software intervention or complex OS involvement
4Quantity of substance
If memory capacity is increased to meet demand, then storage capability is improved, but power consumption during idle states increases
Solution Approach 1:
The patent segments the memory system into two distinct layers: a high-speed volatile DRAM layer for active data and a non-volatile memory layer for data retention during power-off, allowing the system to scale capacity in the non-volatile layer without proportionally increasing idle power consumption
Data Source
AI summary
Some embodiments include apparatuses and electrical models associated with the apparatus. One of the apparatuses includes a power control unit to monitor a power state of the apparatus for entry into a standby mode. The apparatus can include a two-level memory (2LM) hardware accelerator to, responsive to a notification from the power control unit of entry into the standby mode, flush dynamic random access memory (DRAM) content from a first memory part to a second memory part. The apparatus can include processing circuitry to determine memory utilization and move memory from a first memory portion to a second memory portion responsive to memory utilization exceeding a threshold. Other methods systems and apparatuses are described.