Two-Line Serial Interface Protocol for Low Pin Count Communication
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Solution Overview
Problem
Existing serial communication systems in integrated circuits require multiple wires and pins, leading to increased complexity and cost, and often suffer from interference issues, particularly when multiple components share a single interface, necessitating a more efficient two-line point-to-point serial interface with reduced latency and pin count.
Innovation Solution
A two-line serial interface protocol that biases one line to a logical value when not driven, allows the slave circuit to control data transmission, and uses a clock signal to transmit sequences of bits, enabling efficient communication between a master and slave circuit with reduced pin requirements and minimized interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a three-wire SBI interface is used to allow multiple slaves to share one interface, then interface sharing capability is improved, but pin count and device complexity increase due to requiring three pins per interface
Solution Approach 1:
The patent combines bidirectional data transmission and clock signaling into a single shared wire. The data wire carries both data signals and clock synchronization information by utilizing different voltage levels and timing states, eliminating the need for separate clock wires and reducing the total pin count while maintaining multi-slave interface sharing capability
Solution Approach 2:
The data wire serves multiple functions: it transmits data bidirectionally between master and slaves, provides clock synchronization through voltage level transitions, and enables slave selection through specific signal patterns. This multi-functional design allows the interface to support multiple slaves with fewer pins than conventional dedicated-clock approaches
2Adaptability or versatility
If additional interfaces are added to support multiple slave devices, then adaptability is improved, but manufacturing cost and die size increase
Solution Approach 1:
The patent merges multiple interface functions into a single physical connection between master and slave devices. By combining data transmission, clock signaling, and slave selection into one wire interface, the design reduces the number of required pads and interconnect structures, directly lowering manufacturing cost and die size while maintaining support for multiple slave devices
Solution Approach 2:
The single wire interface is designed to be universal, supporting multiple slave devices through software-configurable addressing and signal patterns rather than requiring hardware duplication. This approach eliminates the need for additional physical interfaces for each slave, reducing manufacturing complexity and cost
3Reliability
If more wires are used in the interface, then communication reliability is improved, but pin count and device complexity increase
Solution Approach 1:
The patent combines clock synchronization and data transmission into a single wire interface. The master device generates clock signals by transitioning the wire voltage to defined levels, and slave devices detect these same voltage transitions for synchronization while reading data during specific time windows. This merging maintains reliable communication without requiring separate clock and data wires
4Productivity
If a shared interface is used for multiple components, then interface utilization is improved, but interference between components occurs
Solution Approach 1:
The master device preliminarily selects and activates a specific slave device before data transmission begins. By asserting a unique slave selection code on the data wire during a predefined time window, the master ensures that only the intended slave is in a receptive state, preventing interference with other slaves that are ignoring the transmission
Data Source
AI summary
This disclosure includes a point-to-point two-lineserial interface (TSI) suitable for use in a wireless communications device as well as in other applications. The TSI may employ a protocol providing multiple frame formats to achieve delivery of one type of message with a reduced latency and other messages at increased latencies. Further, although the master initiates reads, the slave circuit may signal the master in real time over the TSI.