Two-Part PHY Interface for USB 2.0 on Low-Voltage SoC
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Solution Overview
Problem
Modern System-on-Chip (SoC) devices face a challenge in supporting USB 2.0 connectivity using cutting-edge technology nodes, as these nodes cannot support the legacy voltage requirements of the USB 2.0 protocol, particularly the 3.3V voltage swing, while conventional USB 2.0 PHY designs are incompatible with low-voltage nodes.
Innovation Solution
A two-part PHY configuration is introduced, where a low-voltage PHY portion is integrated into the SoC device using cutting-edge technology nodes and a high-voltage PHY portion is integrated into the power management device, allowing for the attenuation of incoming 3.3V signals to 1.8V or less, enabling legacy 3.3V operations without requiring 3.3V sources on the SoC device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional USB 2.0 PHY designs are used, then USB 2.0 compliance is achieved, but compatibility with cutting-edge low-voltage technology nodes is lost
Solution Approach 1:
The PHY is divided into two separate portions: a low-voltage PHY portion integrated into the SoC and a high-voltage PHY portion integrated into the PMD. This segmentation allows each portion to be optimized for its specific voltage requirements, enabling USB 2.0 compliance while maintaining compatibility with cutting-edge low-voltage technology nodes.
Solution Approach 2:
The PMD acts as an intermediary between the low-voltage SoC and the high-voltage USB interface. It receives attenuated signals from the SoC, restores them to the required voltage levels, and transmits them to the USB receptacle, thereby bridging the voltage incompatibility between cutting-edge technology nodes and legacy USB protocols.
2Reliability
If high-voltage PHY portion is integrated into the SoC, then legacy 3.3V operations are supported, but production costs and design complexity increase
Solution Approach 1:
By separating the high-voltage PHY portion from the SoC and integrating it into the PMD instead, the design leverages existing PMD capabilities and avoids the need to modify SoC fabrication processes, thereby reducing production costs and design complexity while still supporting legacy 3.3V operations.
Solution Approach 2:
The PMD is designed to perform multiple functions: power management for the SoC and high-voltage signal transmission for USB communication. This multi-functionality eliminates the need for a separate high-voltage PHY integration into the SoC, reducing overall system complexity and manufacturing costs.
3Adaptability or versatility
If signal attenuation from 3.3V to 1.8V is implemented, then low-voltage SoC compatibility is achieved, but additional signal processing requirements are introduced
Solution Approach 1:
The PMD serves as an intermediary that handles the signal attenuation and restoration process. It receives 3.3V signals from the USB interface, attenuates them to 1.8V for the low-voltage SoC, and vice versa for outgoing signals. This centralized signal processing in the PMD minimizes additional complexity in the SoC design.
Solution Approach 2:
The system dynamically changes the voltage parameter of the USB data signals based on the operating mode. During USB transactions, the PMD converts between 3.3V (for USB compatibility) and 1.8V (for low-voltage SoC compatibility), enabling the system to adapt to different voltage requirements without requiring separate hardware designs.
Data Source
AI summary
A two-part interface PHY configuration includes a low-voltage PHY portion configured for instantiation on an SoC device fabricated using a cutting-edge technology node, and a high-voltage PHY portion configured for instantiation on a power management device (PMD) fabricated using a high-voltage technology node. The low-voltage PHY portion includes interface control and low-voltage I/O circuitry configured to transfer outgoing 3.3V data signals to the high-voltage PHY portion at low voltage levels, and the high-voltage PHY portion includes a driver circuit that retransmits the low-voltage data signals onto a bus at the required 3.3V level. Incoming 3.3V data signals pass through an attenuator circuit before being processed using a receiver circuit provided on the low-voltage PHY portion. In USB applications, outgoing USB High Speed data signals are generated by a driver circuit provided on a low-voltage USB PHY portion.