Two-Phase Bias Circuit for Memory Bit Line Precharge Overshoot
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Solution Overview
Problem
The complexity and space requirements of biasing structures in integrated circuit memory devices limit their size, speed, and power efficiency, particularly as memory access speeds increase and power supply voltages drop, leading to overshoot during precharge intervals that can reduce data sensing accuracy.
Innovation Solution
A two-phase bias circuit is implemented using clamp transistors, a precharge transistor, a cascode transistor, and a resistive element in series, with a feedback circuit responsive to timing signals to set first and second bias levels during the precharge interval, preventing voltage overshoot on data lines and optimizing layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If complex biasing structures are used on every bit line to enable fast precharge, then precharge speed is improved, but device complexity and layout area increase
Solution Approach 1:
Multiple bit lines share a common biasing structure rather than each bit line having its own independent biasing circuit. The clamp transistors and feedback inverters are shared across multiple bit lines, reducing overall device complexity while maintaining fast precharge capability.
Solution Approach 2:
The biasing structure is designed to serve multiple functions: precharging multiple bit lines simultaneously, providing voltage regulation, and enabling parallel operation. The feedback inverter circuit performs both sensing and biasing functions.
2Speed
If higher bias levels are applied during precharge to speed up the process, then precharge speed is improved, but voltage overshoot increases reducing sensing margin
Solution Approach 1:
The precharge process is divided into two phases with different bias levels. During the first phase, a higher bias level is applied to quickly charge the bit line. During the second phase, a lower bias level is applied to prevent overshoot and maintain sensing margin. This periodic adjustment of bias levels optimizes both speed and reliability.
Solution Approach 2:
Feedback inverters are used to dynamically adjust the bias voltage applied to clamp transistors during precharge. The feedback mechanism monitors the bit line voltage and adjusts the bias level accordingly, preventing overshoot while maintaining fast precharge speed.
Data Source
AI summary
An integrated circuit includes an array of memory cells with a plurality of columns and rows. A plurality of data lines is coupled to the columns in the array and a plurality of word lines is coupled to the rows in the array. Clamp transistors are coupled to respective data lines in the plurality of data lines, and adapted to prevent voltage on the respective bit lines from overshooting a target level during a precharge interval. A bias circuit is coupled to the clamp transistors on the plurality of bit lines, and arranged to apply the bias voltage in at least two phases within a precharge interval, and to prevent overshoot of the target level on the bit line.