Two-Phase Clock Generation for Symmetric Charge Pump Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing circuit applications face challenges in generating symmetric two-phase non-overlapping clock signals, which are crucial for efficient power conversion in charge pumps, as existing methods often result in asymmetrical waveforms leading to suboptimal power conversion efficiency.
Innovation Solution
A clock generation circuit utilizing a delay circuit and an inverter to generate non-inverted and inverted clock signals based on a single input clock signal, with the delay circuit set to improve symmetry, ensuring that the waveforms of the generated clock signals have minimal duration differences, thereby enhancing power conversion efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional clock signal generation methods are used, then the circuit complexity is low, but the waveform symmetry is poor leading to suboptimal power conversion efficiency
Solution Approach 1:
The clock generation circuit is segmented into distinct functional blocks: an inverter stage for signal inversion, a delay circuit for timing adjustment, and a non-overlapping clock generation stage. This segmentation allows each component to be optimized independently for its specific function while maintaining overall waveform symmetry and reducing power loss.
2Productivity
If asymmetric clock signals are generated, then the device complexity is reduced, but the power conversion efficiency deteriorates
Solution Approach 1:
The delay circuit introduces a controlled time delay to the inverted clock signal, creating a feedback mechanism that adjusts the timing of clock phases. This feedback approach ensures that the rising and falling edges of the non-overlapping clock signals are symmetrically positioned, maximizing power conversion efficiency in charge pump applications.
3Manufacturing precision
If a delay circuit is added to improve clock signal symmetry, then the waveform symmetry is improved, but the device complexity increases
Solution Approach 1:
The delay circuit modifies the time domain parameter of the clock signal by introducing a precise delay period. This parameter change allows adjustment of the clock phase timing to achieve symmetric waveforms with minimal overlap, improving power conversion efficiency without requiring complex circuit topologies.
Data Source
AI summary
A clock generation circuit includes: a two-phase clock generation circuit configured to generate a first phase clock signal and a second phase clock signal based correspondingly on a non-inverted clock signal and an inverted clock signal; an inverter configured to generate the inverted clock signal based on an input clock signal; and a delay circuit which is non-inverter-based and which is configured to generate the non-inverted clock signal based on the input clock signal, the delay circuit having a predetermined delay sufficient to induce symmetry in the first and second phase clock signals such that durational midpoints of overlapping opposite phases of the first and second phase clock signals are substantially aligned.