Two-Phase Latch Clocking for Hold-Time Violation Elimination
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Solution Overview
Problem
Conventional circuits using edge-triggered flip-flops often experience hold time violations, leading to the unnecessary insertion of additional circuitry to address these issues, which occupies space and consumes power.
Innovation Solution
Converting the circuit design to use two-phase non-overlapping clocking by replacing edge-triggered flip-flops with pairs of latches and determining a midpoint for the combinational logic circuit, allowing two-phase non-overlapping clock signals to be provided to the latches, thereby eliminating hold time violations and reducing sensitivity to clock jitter and skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If edge-triggered flip-flops are used for pipelining, then sequential logic can be implemented, but hold time violations occur when logic delay approaches hold time requirements
Solution Approach 1:
The patent segments the single clock phase into two non-overlapping phases (phi1 and phi2), creating separate master and slave latch periods. This segmentation allows the circuit to operate in distinct time windows where data is captured during one phase and transferred during the other, eliminating hold time violations without requiring additional corrective circuitry.
Solution Approach 2:
The patent introduces dynamic clocking where the clock signal is divided into two dynamically alternating phases. The master latch is enabled during phi1 while the slave latch is enabled during phi2, creating a dynamic time-multiplexed operation that adapts to the logic delay characteristics without requiring static additional circuitry.
2Reliability
If additional circuitry is inserted to fix hold time violations, then hold time compliance is improved, but die area and power consumption increase
Solution Approach 1:
By segmenting the clock signal into two phases and using master-slave latches, the patent achieves hold time compliance through temporal separation rather than spatial addition of circuitry. The same latch structure serves dual purposes across different time phases, eliminating the need for additional hold-time-fixing circuitry that would occupy die area.
Solution Approach 2:
The patent employs periodic alternating activation of master and slave latches driven by non-overlapping clock phases. This periodic action ensures that data is always captured and transferred at appropriate times without requiring additional circuitry, as the timing itself is structured to prevent hold time violations.
3Reliability
If additional circuitry is inserted to fix hold time violations, then hold time compliance is improved, but power consumption increases
Solution Approach 1:
The patent segments operation into two phases where only one latch is active at a time. This segmentation reduces power consumption compared to using additional circuitry continuously, as the master and slave latches share the workload temporally rather than requiring redundant circuitry to be always active.
Solution Approach 2:
By using periodic alternating activation of latches with non-overlapping clock phases, the patent reduces average power consumption. The periodic nature ensures that critical path elements are not continuously active, and the two-phase structure eliminates the need for additional power-consuming hold-time-fixing circuitry.
4Device complexity
If edge-triggered clocking is used, then simple clocking is achieved, but the circuit is sensitive to clock jitter and skew
Solution Approach 1:
The patent segments the clocking into two non-overlapping phases, which provides timing margins against jitter and skew. By capturing data during one phase and transferring during the other, the circuit gains inherent immunity to timing variations that would affect single-phase edge-triggered operation.
Solution Approach 2:
The dynamic two-phase clocking structure adapts to timing variations by providing separate capture and transfer windows. This dynamic operation allows the circuit to tolerate clock jitter and skew better than static edge-triggered flip-flops, as the non-overlapping phases create built-in timing margins.
Data Source
AI summary
A system, method, and computer program product for converting a design from edge-triggered docking to two-phase non-overlapping clocking is disclosed. The method includes the steps of replacing an edge-triggered flip-flop circuit that is coupled to a combinational logic circuit with a pair of latches including a first latch circuit and a second latch circuit and determining a midpoint of the combinational logic circuit based on timing information. The second latch circuit is propagated to a midpoint of the combinational logic circuit and two-phase non-overlapping clock signals are provided to the pair of latches.