Two-Phase Memory Cell Programming to Reduce Disturb
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Solution Overview
Problem
Multilevel cell (MLC) flash memory devices face significant disturbance issues during programming, particularly for cells programmed to lower levels, due to high voltage pulses used for programming higher levels, leading to potential data errors and reduced reliability.
Innovation Solution
The method involves splitting data programming into two or more steps, where cells programmed to higher levels are initially programmed using overlapping voltage ranges, and cells programmed to lower levels are inhibited or programmed using reduced voltage pulses to minimize disturbance, thereby reducing the number of high-voltage pulses applied to lower level cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high voltage pulses are used to program cells to higher levels, then programming speed is improved, but cell disturbance increases leading to data errors
Solution Approach 1:
The programming process is divided into two distinct phases: a first programming phase that programs cells to higher levels using high voltage pulses, and a second programming phase that programs cells to lower levels using reduced voltage pulses. This segmentation allows the high voltage pulses to be applied only during the first phase, reducing their cumulative effect on lower level cells while maintaining programming speed.
Solution Approach 2:
Cells are pre-categorized into higher levels and lower levels before programming begins. The higher level cells are programmed first using high voltage pulses, establishing their final state before any subsequent programming operations. This preliminary action ensures that lower level cells are not subjected to prolonged exposure to high voltage pulses that would cause disturbance.
2Manufacturing precision
If high voltage pulses are applied repeatedly to program higher level cells, then programming completeness is improved, but disturbance to lower level cells increases
Solution Approach 1:
The programming operation is segmented into two sequential phases with distinct voltage characteristics. The first phase uses high voltage pulses (e.g., 18-24V) exclusively for programming higher level cells, while the second phase uses reduced voltage pulses (e.g., 12-18V) for programming lower level cells. This segmentation ensures that high voltage pulses are applied only when necessary for higher level programming, minimizing harmful effects on lower level cells.
Solution Approach 2:
Different voltage pulse characteristics are applied locally to different cell groups based on their target levels. Higher level cells receive high voltage pulses during the first phase, while lower level cells receive reduced voltage pulses during the second phase. This local quality approach ensures that each cell group receives the appropriate voltage level for its programming needs, avoiding unnecessary exposure to high voltage pulses.
3Adaptability or versatility
If voltage ranges overlap for programming different levels, then programming flexibility is improved, but disturbance to lower level cells increases
Solution Approach 1:
The voltage range usage is segmented across two phases: the first phase utilizes overlapping voltage ranges (e.g., 18-24V) for programming higher level cells, while the second phase uses a non-overlapping reduced voltage range (e.g., 12-18V) for programming lower level cells. This segmentation maintains programming flexibility during the first phase while protecting lower level cells during the second phase.
Solution Approach 2:
The voltage range strategy is predetermined: overlapping voltage ranges are reserved for the first phase when programming higher level cells, while reduced non-overlapping voltage ranges are prepared in advance for the second phase. This preliminary planning of voltage range allocation allows flexible programming of higher levels without exposing lower level cells to harmful overlapping voltage pulses.
Data Source
AI summary
Memory devices are disclosed. A memory device may include control logic configured to program a first number of memory cells to a level greater than or equal to a first particular level and inhibit programming of a second number of memory cells while the first number of memory cells is programmed. The control logic may also be configured to program the second number of memory cells to a level less than the first particular level and inhibit programming of the first number of memory cells while the second number of memory cells is programmed. Associated methods are also disclosed.