Two-Phase Shift Register Clocking for Hold Time Immunity
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Solution Overview
Problem
Focal plane arrays face challenges in efficiently managing clock signals for shift registers, leading to hold time violations and increased circuitry complexity, which affects the size, power consumption, and cost of digital pixels.
Innovation Solution
Implementing a two-phase non-overlapping clock system for shift registers, where one clock signal controls master latches and another controls slave latches, eliminating the need for buffers and reducing circuit complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If buffers are placed between master latches and slave latches to prevent hold time violations, then reliability is improved, but device complexity increases
Solution Approach 1:
The clock signal is segmented into two distinct phases (first clock phase and second clock phase) that are non-overlapping in time. This segmentation allows master latches and slave latches to operate in separate time windows, eliminating the need for buffers while ensuring proper hold time compliance. Each latch type responds to its designated clock phase, creating temporal separation that prevents signal conflicts.
Solution Approach 2:
The shift register operates using periodic clock phases that alternate in a regular pattern. The first clock phase activates master latches while the second clock phase activates slave latches, creating a rhythmic operation cycle. This periodic action ensures that data is transferred from master to slave latches in a controlled manner without requiring additional buffering circuitry.
2Reliability
If buffers are added between master and slave latches to ensure proper timing, then reliability is improved, but power consumption increases
Solution Approach 1:
The clocking system is segmented into two non-overlapping phases that selectively activate different latch groups. This segmentation eliminates the need for continuous buffering operations, reducing power consumption while maintaining timing control. Each phase drives specific latches only when needed, avoiding unnecessary power dissipation in buffer circuits.
Solution Approach 2:
The periodic alternation between first and second clock phases creates an efficient operating cycle where buffers are not continuously active. Power is consumed only during the actual latch transitions rather than continuously, significantly reducing overall power consumption while maintaining reliable timing control through the periodic clock structure.
3Reliability
If delay elements are inserted between master and slave latches to resolve hold time issues, then reliability is improved, but device complexity increases
Solution Approach 1:
Instead of adding spatial delay elements, the invention segments the clock signal into two non-overlapping phases. This temporal segmentation provides hold time immunity by ensuring that slave latches are activated only after master latches have completed their transition, without requiring any additional physical delay components in the signal path.
Solution Approach 2:
The periodic clock phases create a natural timing sequence where data flows from master to slave latches in discrete steps. This periodic action inherently provides the necessary delay and synchronization without additional circuit elements, maintaining simplicity while ensuring reliable hold time compliance through the rhythmic clock structure.
Data Source
AI summary
According to one embodiment, a method includes generating a first clock signal and a second clock signal with non-overlapping clock phases. The method may further include latching, by a plurality of master latches of a shift register, a plurality of values at a plurality of inputs of the master latches in response to a particular type of logical transition of the first clock signal. The method also includes latching, by a plurality of slave latches of the shift register, a plurality of output values of the plurality of master latches at a plurality of inputs of the slave latches in response to a particular type of logical transition of the second clock signal.