Two-Plane NAND Flash ECC Using Cross-Page Error Correction
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Solution Overview
Problem
Flash memory devices face increased fault rates due to physical limitations and floating gate faults, leading to inefficiencies in error correction, especially when the number of error bits exceeds the error correctability of existing error correction codes, which can compromise memory credibility and reduce capacity by increasing ECC length.
Innovation Solution
A two-plane error correction method that generates and utilizes both inner and cross correction codes across two pages to enhance error correctability without increasing the length of the error correction code, leveraging the concurrent read/write feature to mix and leverage encoding/decoding of error correction codes between distinct blocks in different planes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the length of the error correction code is increased to enhance error correctability, then the error correctability is improved, but the memory capacity is reduced
Solution Approach 1:
The patent merges the error correction functionality across two pages by generating cross-page correction codes that protect both pages simultaneously. The first correction code protects the first page and part of the second page, while the second correction code protects the second page and part of the first page, effectively combining their protection capabilities without increasing individual code lengths.
Solution Approach 2:
Each correction code serves multiple functions: the first correction code corrects errors in the first page and assists in correcting errors in the second page, while the second correction code corrects errors in the second page and assists in correcting errors in the first page. This multi-functionality allows the same code length to provide enhanced overall error protection.
2Reliability
If the error correctability is enhanced by increasing the ECC length, then more error bits can be corrected, but the overall memory capacity decreases
Solution Approach 1:
The patent combines the error correction capabilities across two pages by implementing cross-page correction codes. The first correction code (n/2 bytes) protects the first page and the second correction code (n/2 bytes) protects the second page, while both codes work together to provide enhanced error correction for both pages without increasing the total ECC length.
3Device complexity
If a single ECC code is used for each page, then the implementation is simple, but the error correctability is insufficient when error bits exceed T
Solution Approach 1:
The patent segments the error correction code into two parts: an inner correction code (n/2 bytes) that provides basic error correction for each page, and a cross correction code (n/2 bytes) that provides additional error correction capability by leveraging information from the other page. This segmentation allows the system to maintain simplicity while enhancing error correctability.
Data Source
AI summary
In order to correct errors of a first page on one plane in a two-plane NAND flash memory, use data of a second page on another plane to mix the encoding and leverage the error correction code of the first page. Each of the error correction codes of the first page and the second page is divided into an inner correction code and a cross correction code. The inner correction codes are used to correct errors of their own pages and the cross correction codes are used to correct errors of two distinct groups, grouped from the even and odd bytes of the two pages respectively. The second page, with fewer errors, is therefore used to enhance the correcting ability of the first page, without lengthening the error correction code of the first page.