Two-Point PLL Modulator for Variable Reference Frequencies
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Solution Overview
Problem
Two-point modulators face challenges in multiple clock systems, particularly in mobile radio systems, where maintaining a constant clock frequency for digital signal processors while allowing variable reference frequencies for PLLs is necessary to ensure stable phase and amplitude matching of modulation signals, which is difficult due to the need for spectral purity and noise response optimization.
Innovation Solution
A two-point modulator arrangement with a phase comparator, frequency divider, digital signal processor, and digital filter, where the digital filter operates at a constant clock frequency generated by a frequency generation block, independent of the PLL's reference frequency, and a sigma-delta modulator synchronized with the PLL's reference frequency, ensuring no resynchronization is needed between the digital signal processor and digital filter, and maintaining high spectral purity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the digital signal processor and digital filter are designed for a particular clock frequency to ensure stable phase and amplitude matching, then the spectral purity is improved, but the adaptability to different reference frequencies deteriorates
Solution Approach 1:
The system is divided into two independent frequency domains: a fixed clock domain for the digital signal processor and digital filter, and a variable reference frequency domain for the PLL. This segmentation allows each component to operate optimally in its designated frequency domain without interfering with the other's performance characteristics.
Solution Approach 2:
A frequency divider with adjustable division ratio serves as an intermediary between the fixed clock domain and the variable reference frequency domain. By adjusting the division ratio, the system can adapt to different reference frequencies while maintaining the stability of the digital signal processing components.
2Object-affected harmful factors
If the control loop bandwidth is designed to be much smaller than the modulation data bandwidth, then the noise response is optimized, but the response speed of the modulation compensation deteriorates
Solution Approach 1:
The system employs dynamic two-point modulation where the analog modulation signal continuously compensates for the limitations of the narrow control loop bandwidth. This dynamic adjustment allows the system to maintain low noise response while achieving adequate modulation response through the combined effect of digital and analog modulation paths.
Solution Approach 2:
The system changes the modulation approach by using dual-point modulation with both digital (frequency divider) and analog (oscillator input) modulation signals. This parameter change enables the system to achieve both low noise and adequate response speed by leveraging the complementary strengths of both modulation paths.
3Measurement precision
If phase equality and amplitude matching are ensured for analog and digital modulation signals, then the spectral purity is improved, but the device complexity increases
Solution Approach 1:
The system merges the digital modulation path through the frequency divider and the analog modulation path at the oscillator input into a unified two-point modulation scheme. This combination allows the system to achieve high spectral purity through coordinated control of both paths while sharing common control logic and signal sources.
Solution Approach 2:
The digital signal processor and digital filter serve multiple functions: they generate both the digital modulation signal for the frequency divider and the reference signal for the analog modulation path. This multi-functionality reduces the need for separate dedicated components for phase and amplitude matching.
Data Source
AI summary
The present invention provides a two-point modulator arrangement with a PLL that can be operated at various reference frequencies. A modulation signal provided by a digital signal processor is supplied as an analog signal at the input of the oscillator in the PLL and as a digital modulation signal on a frequency divider. For the purpose of pulse shaping the digital modulation data, a digital filter is provided that is coupled to the control input of the frequency divider and, in line with the principle proposed, is operated at the same, constant clock frequency as the signal processor, regardless of the reference frequency. As a result, no resynchronization of the digital modulation data is necessary upstream of the digital filter.