2-Port SRAM CFET Layout for Compact 3D Transistor Cells
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Solution Overview
Problem
There is a lack of specific consideration for the layout configuration of a 2-port SRAM cell using a Complementary FET (CFET) with three-dimensional transistors, which leads to inefficiencies in area utilization and increased power consumption.
Innovation Solution
A 2-port SRAM cell is configured using eight three-dimensional transistors, with specific layering and alignment of transistors to reduce area, including a first and second conductive type transistors stacked in different layers and aligned in specific directions, forming a CFET layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional planar transistors are used for SRAM cell layout, then manufacturing process is simpler, but area utilization is inefficient and power consumption increases
Solution Approach 1:
The patent transitions from traditional planar (2D) transistor layouts to three-dimensional stacked transistor configurations. Multiple transistor layers are stacked vertically, with upper-layer transistors positioned above lower-layer transistors, enabling efficient area utilization while reducing the footprint of the SRAM cell. This dimensional change allows achieving both compact area and functional complexity.
2Productivity
If transistor scaling is continued to improve integration degree, then operating speed improves, but off-current increases and power consumption rises
Solution Approach 1:
Instead of continuing horizontal scaling which increases off-current, the patent employs vertical stacking of transistors in multiple layers. This three-dimensional configuration maintains smaller transistor footprints for high integration and fast operation, while the vertical architecture provides better control over off-current through improved gate control and reduced leakage paths, thereby lowering power consumption.
Solution Approach 2:
The patent implements different conductive types (n-type and p-type) in specific spatial locations within the stacked structure. By strategically placing n-type and p-type transistors in upper and lower layers with specific connectivity patterns, the design optimizes local electrical characteristics to reduce off-current while maintaining high-speed operation.
3Area of stationary object
If three-dimensional stacked transistor configuration is used, then area is reduced, but layout design complexity increases
Solution Approach 1:
The patent systematically organizes transistors into upper and lower layers with defined stacking relationships. Each layer contains transistors of specific conductive types positioned at predetermined locations, with inter-layer connections established through vertical conductors. This structured approach to three-dimensional layout design enables area reduction while maintaining manufacturability through repeatable patterns.
Data Source
AI summary
Transistors (N1 to N12) corresponding to drive transistors (PD1, PD2), access transistors (PG1, PG2), read drive transistor (RPD1), and read access transistor (RPG1) are formed in a lower portion of a cell. Transistors (P1, P2) corresponding to load transistors (PU1, PU2), respectively, are formed in an upper portion of the cell. The transistors (P1, P2) overlap the transistors (N3, N8), respectively, in plan view.