Two-Port SRAM Readout Using Dummy RBL Latch Timing
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Solution Overview
Problem
Existing 2P-SRAMs face challenges in reducing power dissipation and improving read stability, particularly in high-bandwidth memory applications, due to the need for bit line keepers which slow down discharge speed and increase delay overhead as supply voltage decreases.
Innovation Solution
A 2P-SRAM bit cell design that includes a dummy column circuit to monitor RBL discharge speed, generates a latch enable signal, and uses a pseudo differential amplifier to amplify the RBL signal, eliminating the need for a bit line keeper and optimizing RWL voltage for process and temperature variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a bit line keeper is used to improve read stability, then read stability is improved, but discharge speed decreases and delay overhead increases
Solution Approach 1:
The patent removes the bit line keeper circuit from the traditional 2P-SRAM structure. Instead of using a bit line keeper to maintain read stability, the invention uses a latch-based readout mechanism that captures data from the read bit line without requiring continuous retention circuitry, thereby eliminating the discharge speed penalty associated with bit line keepers.
Solution Approach 2:
The patent employs a latch enable signal that is activated in advance of the read operation to prepare the latch circuit for data capture. This preliminary action ensures that the latch is ready to capture the read bit line data immediately when the read signal is applied, eliminating the need for bit line keepers and improving discharge speed while maintaining read stability.
2Loss of energy
If supply voltage is reduced to lower power dissipation, then power dissipation is reduced, but discharge speed decreases and delay overhead increases
Solution Approach 1:
The patent implements dynamic voltage control where the supply voltage is adjusted based on operational conditions. The adaptive voltage supply circuit increases voltage during write operations to ensure fast discharge and maintains lower voltage during read operations to minimize power dissipation, thereby dynamically optimizing the trade-off between speed and power consumption.
Solution Approach 2:
The patent changes the voltage parameter dynamically during different operational phases. During write operations, the supply voltage is raised to enable fast discharge of the read bit line, while during read operations, the voltage is reduced to minimize power dissipation. This parameter change allows the system to achieve both low power dissipation and fast discharge speed at different times.
3Device complexity
If traditional 2P-SRAM structure is used, then device complexity is low, but read stability deteriorates and power dissipation increases
Solution Approach 1:
The patent merges the read stability function into the latch-based readout mechanism rather than using a separate bit line keeper circuit. The latch circuit combines the functions of data capture and retention, eliminating the need for additional retention circuitry and maintaining low device complexity while improving read stability.
Solution Approach 2:
The latch circuit in the patent is designed to automatically capture and hold the read bit line data without requiring external bit line keeper circuits. The latch enable signal automatically triggers the latch to capture data, and the latch self-maintains the data until explicitly cleared, providing self-service read stability without additional complexity.
Data Source
AI summary
A low-power two-port static random access memory (2P-SRAM) for at-memory architecture is set forth. Each column has a latch which is controlled by Latch_EN signal which is generated by monitoring the discharge speed of dummy read bit line (dummy RBL). The write scheme uses boosted write word line with only a short MOS between write bit line (WBL) and write bit line bar (/WBL) to generate half Vdd write bit line precharge. The read word line voltage is supplied by adaptive voltage supply which can compensate process and temperature variation. The segmented number of WBL is equal or larger than that of RBL.