Two-Port SRAM Cell Structure With Node Isolation for Lower RC Delay
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing sheet resistance of metal lines in SRAM cells due to down-scaling leads to higher RC delay, hindering improvements in read and write speed.
Innovation Solution
A two-port SRAM cell structure with node-decoupling structures, such as isolation transistors or dielectric gates, decoupling storage nodes from neighboring cells, combined with optimized layout and metal line placement to reduce resistance and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If SRAM cells are down-scaled to increase density, then device area is reduced, but sheet resistance of metal lines increases causing higher RC delay
Solution Approach 1:
The patent transitions from planar metal line routing to three-dimensional vertical interconnect structures. By stacking metal lines and using via connections between different metal layers, the design reduces the horizontal distance electrons must travel, thereby reducing RC delay while maintaining small footprint. The bit lines and word lines are routed across multiple metal layers (M1-M4) to optimize signal paths.
Solution Approach 2:
The SRAM cell is divided into functionally separate regions with dedicated metal line segments for different purposes. Bit lines (BL, BLB) and word lines (WL, WLB) are segmented and routed through different metal layers. Isolation transistors are placed at specific segments to decouple neighboring cells, reducing capacitive coupling effects that would increase delay.
2Quantity of substance
If metal line dimensions are reduced to fit more cells, then density increases, but resistance of metal lines increases causing higher RC delay
Solution Approach 1:
The patent uses multiple metal layers (M1, M2, M3, M4) to route bit lines and word lines in three dimensions. This vertical stacking allows longer effective conductor length without increasing planar footprint, compensating for the higher resistance of narrower lines. Via connections provide low-resistance vertical pathways between layers.
Solution Approach 2:
The interconnect structure employs composite material approaches by combining different metal layers with varying properties. Lower metal layers (M1, M2) may use materials optimized for certain current densities while upper layers (M3, M4) use materials optimized for signal speed. The combination of metal interconnects with dielectric materials of specific permittivity also forms a composite transmission line structure.
3Speed
If isolation structures are added to decouple storage nodes, then RC delay is reduced, but device complexity increases
Solution Approach 1:
The isolation transistors are merged with the regular SRAM cell transistor array, using the same fabrication processes and layout patterns. The isolation transistors share common diffusion regions, gate structures, and metal interconnects with the storage transistors. This integration approach adds decoupling functionality without requiring separate processing steps or significantly increasing cell area.
Solution Approach 2:
The isolation transistors serve multiple functions: they decouple storage nodes from neighboring cells to reduce capacitive coupling and RC delay, they provide additional current paths for read/write operations, and they maintain uniform gate density across the cell array. The same transistor structure is used for both isolation and functional purposes.
Data Source
AI summary
A circuit includes a Vdd node, and a two-port Static Random-Access Memory (SRAM) cell pair having a first SRAM cell and a second SRAM cell having a same structure. The first SRAM cell is a ten-transistor SRAM cell that comprises a first pull-up transistor and a second pull-up transistor, a first pull-down transistor and a second pull-down transistor forming a latch with the first pull-up transistor and the second pull-up transistor, a first pass-gate transistor and a second pass-gate transistor connecting to the latch, a p-type isolation transistor including a first source/drain region connecting to a drain region of the first pull-up transistor, and a gate connecting to the Vdd node. The circuit further includes a read bit-line shared with the second SRAM cell. and a write bit-line pair connecting to gates of the first pass-gate transistor and the second pass-gate transistor.