Two-Port 8T SRAM Cell with Short Pass-Gate Transistors
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Solution Overview
Problem
Conventional 6T SRAM cells face challenges in reducing power consumption while maintaining cell stability and operation speed, especially in system-on-chip applications where reducing operation voltage is limited by the required static noise margin (SNM), and the processor cannot be turned off to access level-1 cache memory.
Innovation Solution
A two-port static random access memory (SRAM) cell design with a first and second half write-port and a read-port, featuring pass-gate transistors with shorter channel lengths than pull-down transistors, allowing for reduced operation voltage without compromising stability or speed, and optimized transistor formation processes to enhance drivability and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If operation voltage is reduced to lower power consumption, then power consumption is reduced, but cell stability deteriorates due to reduced static noise margin
Solution Approach 1:
The patent applies local quality by differentiating transistor characteristics within the SRAM cell. Specifically, the pass-gate transistors have shorter channel lengths compared to the pull-up and pull-down transistors, creating localized performance optimization in the access path while maintaining overall cell stability through the longer-channel transistors that provide sufficient drive strength and noise margin.
Solution Approach 2:
The patent changes the channel length parameter of the pass-gate transistors to be shorter than that of the pull-up and pull-down transistors. This parameter change enables the cell to operate at lower voltages by optimizing the trade-off between access speed and stability, allowing reduced power consumption without sacrificing cell stability.
2Speed
If operation voltage is reduced to increase speed, then operation speed is improved, but power consumption increases due to reduced static noise margin
Solution Approach 1:
The pass-gate transistors are designed with shorter channel lengths to provide fast access paths for reading and writing operations, while the pull-up and pull-down transistors maintain longer channel lengths to ensure sufficient drive strength and noise margin at reduced voltages, enabling both speed and low power consumption.
Solution Approach 2:
By changing the channel length parameter of pass-gate transistors to be shorter than pull-up and pull-down transistors, the patent achieves faster operation speed while maintaining stability at lower voltages, thereby reducing power consumption without sacrificing speed.
3Ease of operation
If processor is kept on to access L1 cache, then access capability is maintained, but power consumption cannot be reduced
Solution Approach 1:
The SRAM cell is designed with optimized transistor parameters, specifically shorter channel lengths for pass-gate transistors, enabling it to operate at the same voltage level as the processor. This allows the L1 cache to run at processor voltage without requiring the processor itself to run at higher voltages, thereby enabling power reduction while maintaining access capability.
Data Source
AI summary
An integrated circuit includes a two-port static random access memory (SRAM) cell, which includes a first half write-port, a second half write-port, and a read-port. The first half write-port includes a first pull-up transistor, a first pull-down transistor, and a first pass-gate transistor interconnected to each other. The second half write-port includes a second pull-up transistor, a second pull-down transistor, and a second pass-gate transistor interconnected to each other and to the first half write-port. Channel lengths of the first pass-gate transistor and the second pass-gate transistor are less than channel lengths of the first pull-down transistor and the second pull-down transistor. The read-port includes a read-port pull-down transistor connected to the first half write-port, and a read-port pass-gate transistor connected to the read-port pull-down transistor.