Two-Rail Level Shifter Circuit With Leakage Cutoff Control
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Solution Overview
Problem
Level shifters face challenges in efficiently converting both high and low power supply voltage levels while minimizing static power and leakage current, particularly in reducing the number of power supply rails to alleviate routing congestion and extend battery life.
Innovation Solution
A level shifter circuit design utilizing a P channel configuration for high voltage logic level shifting and N channel transistors for low voltage conversion, with an enabling circuit to cut off leakage current paths and enhance speed, operating with only two power supply rails (VDD and VSS) to reduce routing congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a level shifter converts both logic high and logic low levels simultaneously, then speed is improved, but static power consumption increases due to current paths to ground
Solution Approach 1:
The level shifter uses dynamic control of transistor switching states to enable simultaneous conversion of both logic high and low levels while preventing steady-state current paths. The circuit transitions between different conduction states based on input signals, achieving high-speed operation without continuous power dissipation.
Solution Approach 2:
The circuit employs feedback mechanisms through cross-coupled transistors that monitor and adjust the conduction states. This feedback ensures that current paths are opened or closed based on the actual signal levels, preventing static power consumption while maintaining fast switching performance.
2Adaptability or versatility
If multiple power supply rails are used in level shifter design, then voltage level conversion flexibility is improved, but routing congestion increases
Solution Approach 1:
The level shifter achieves multiple voltage level conversions using only two power supply rails (VDD and VSS). The circuit is designed to handle different voltage domains through clever transistor configuration rather than requiring separate power rails for each voltage level, thereby reducing routing congestion while maintaining versatility.
Solution Approach 2:
The invention changes the approach from using multiple power supply voltage parameters to using a single power supply voltage with dynamic transistor control. By changing the control parameter from power rail voltage to transistor gate control, the circuit achieves the same functionality with fewer power rails.
3Loss of energy
If transistors are kept in non-conductive state to reduce leakage current, then battery life is extended, but switching speed may be affected
Solution Approach 1:
The circuit prepares transistor states in advance through pre-charging and pre-discharging mechanisms. Before switching occurs, the transistors are positioned in optimal states that minimize leakage while being ready for rapid transition, thus extending battery life without sacrificing switching speed.
Solution Approach 2:
The level shifter uses periodic switching patterns that keep transistors in non-conductive states during idle periods to minimize leakage, then rapidly switch to conductive states when signal transitions are detected. This periodic control extends battery life while maintaining fast response when needed.
Data Source
AI summary
A circuit comprises first and second inverters, first, second, third, and fourth transistors, and an enabling circuit. The first and second inverters each have an input terminal for receiving one of the first or second input signals, an output terminal, and first and second supply terminals. The first transistor is coupled to a first power supply terminal, to the output terminal of the second inverter, and to the first inverter. The second transistor is coupled to the first power supply terminal, to the output terminal of the first inverter, and to the first supply terminal of the second inverter. The third and fourth transistor are coupled to the second supply terminals of the first and second inverters, respectively, and each includes a control electrode and a second current electrode. The enabling circuit is for controlling the third and fourth transistors to reduce a leakage current in the circuit.