Two-Stage Address Translation for Virtualized Systems
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Solution Overview
Problem
Existing IOMMU architectures face issues with unpredictable performance, limited scalability, and inability to support virtualization and memory isolation for data-intensive applications like high-definition video, due to large cache requirements, limited address ranges, and lack of bandwidth.
Innovation Solution
A System on Chip (SoC) architecture incorporating a Memory Management Unit (MMU), System MMU (SMMU), Physical Address Table (PAT), and Peripheral Virtualization Unit (PVU), with a routing circuit that routes memory access requests based on addresses and attributes, enabling two-stage address translation and memory isolation across virtual machines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-stage address translation architecture is used, then device complexity is reduced, but performance becomes unpredictable and scalability is limited
Solution Approach 1:
The address translation architecture is segmented into two distinct stages: first stage translation converts virtual addresses to intermediate physical addresses, and second stage translation converts intermediate physical addresses to final physical addresses. This segmentation allows each stage to be independently optimized and managed, improving performance predictability while maintaining manageable complexity through modular design.
Solution Approach 2:
An intermediate physical address space is introduced as a mediator between virtual addresses and final physical addresses. This intermediary layer enables flexible memory management and isolation between virtual machines, allowing the system to achieve better performance characteristics without directly increasing overall system complexity.
2Adaptability or versatility
If large cache size is used in IOMMU, then address translation capability is improved, but device complexity and memory requirements increase
Solution Approach 1:
The translation capability is segmented across two stages, each with its own translation buffer unit (TBU). This allows the system to achieve comprehensive address translation capability while distributing cache requirements across multiple smaller, more manageable units rather than requiring one large cache in a single-stage architecture.
Solution Approach 2:
The system adds a temporal dimension to address translation by using translation buffers that cache intermediate results from the first stage translation. This allows frequently translated addresses to be quickly resolved without requiring large cache sizes, improving capability while controlling complexity.
3Device complexity
If single address space is used, then device complexity is reduced, but memory isolation and virtualization support are lost
Solution Approach 1:
The address space is segmented into multiple independent intermediate physical address spaces, each associated with a specific virtual machine. This segmentation enables memory isolation between virtual machines while maintaining relatively simple management within each isolated space, as each can be managed independently by its own translation contexts.
Solution Approach 2:
The two-stage translation architecture provides multi-functionality by supporting both virtualization (through multiple translation contexts for different VMs) and non-virtualized operation (through a single translation context). The same hardware infrastructure adapts to different operational modes without requiring separate systems.
4Device complexity
If limited address range is used, then device complexity is reduced, but scalability for data-intensive applications is limited
Solution Approach 1:
The system extends the addressable space by introducing an intermediate physical address dimension between virtual and final physical addresses. This additional dimensional layer allows the system to support large address ranges required for data-intensive applications like high-definition video while maintaining manageable complexity through the structured two-stage translation process.
Data Source
AI summary
In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.