Two-Stage Buffer Operations for Memory Write Alignment

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Solution Overview

Problem

Memory systems face inefficiencies in read operations due to die misalignment, particularly when writing data to multi-plane pages, leading to increased latency and processing overhead, especially for large data files spanning multiple pages.

Innovation Solution

Implementing two-stage buffer operations, which include a flush buffer and a temporary buffer, to manage data transfer sizes based on a threshold size equal to the multi-plane page size, ensuring data is written starting at a zero offset and avoiding die misalignment, thereby improving read performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If data is written to multi-plane pages without two-stage buffer operations, then device complexity is reduced, but read latency increases due to die misalignment

Engineering Contradiction:
Improveread latencyVSAvoidbuffer operation complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The write buffer is divided into two distinct buffers: a first buffer for receiving data and a second buffer for storing data aligned to multi-plane page boundaries. This segmentation allows the system to separate the functions of data reception and alignment, ensuring that read operations start at offset zero without requiring complex real-time alignment logic in a single buffer.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary alignment action by pre-processing write data in the first buffer before transferring it to the second buffer. The controller aligns the data to multi-plane page boundaries in advance, so that when read operations occur, the data is already positioned correctly at offset zero, eliminating the need for complex alignment logic during read operations.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If two-stage buffer operations are implemented, then read performance is improved through zero-offset alignment, but processing overhead increases

Engineering Contradiction:
Improveread performanceVSAvoidprocessing overhead
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The two-stage buffer system maintains continuous useful action by keeping both buffers constantly active during write operations. The first buffer continuously receives data from the host, while the second buffer continuously stores aligned data. This continuous operation ensures that when read commands arrive, aligned data is immediately available at offset zero without interruption or additional processing delay.

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

The first buffer acts as an intermediary between the host and the second buffer, providing a temporary holding area for unaligned data. The controller uses this intermediary to perform alignment transformations before data enters the second buffer, isolating the complexity of alignment logic from the read path and enabling fast read operations without repeated alignment processing.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If data alignment to multi-plane page offset zero is enforced, then die misalignment is avoided, but data transfer flexibility is reduced

Engineering Contradiction:
Improvealignment reliabilityVSAvoiddata transfer flexibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The system changes the parameter of data organization by transforming data from its original form in the first buffer into an aligned form in the second buffer. The controller modifies the data's position and arrangement parameters to match the multi-plane page structure, ensuring offset zero alignment. This parameter transformation maintains flexibility in receiving various data sizes from the host while ensuring reliable alignment for storage.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20240319884A1Two-stage buffer operations supporting write commands
Publication Date: 2024.09.26 MICRON TECHNOLOGY INC
  • US20240319884A1 patent drawing
  • US20240319884A1 patent drawing
  • US20240319884A1 patent drawing

AI summary

Methods, systems, and devices for two-stage buffer operations supporting write commands are described. If data is written to a memory device starting at a multi-plane page offset other than zero, the read performance for the data may decrease significantly due to die misalignment. To avoid die misalignment, a memory system may support two buffers for write data: a flush buffer and a temporary buffer. The memory system may determine whether to add received data to the flush buffer, the temporary buffer, or a combination thereof based on a data transfer size and a threshold size. If the data in the temporary buffer satisfies a copy condition, the data in the temporary buffer is copied into the flush buffer. If the data in the flush buffer satisfies a flush condition, the data in the flush buffer is written to the memory device starting at a multi-plane page offset of zero.