Two-Stage CMOS Circuit Layout for Single-Event Transient Hardening
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Solution Overview
Problem
Existing integrated circuits (ICs) in space-and-satellite (S&S) and terrestrial high-reliability (high-rel) applications are vulnerable to single-event effects (SEEs) such as single-event-transients (SETs) due to radiation, leading to errors and potential irreparable damage, with conventional radiation-hardening techniques like transistor up-sizing being impractical due to area and power overheads.
Innovation Solution
A 2-stage circuit arrangement is implemented with transistor insertion-cum-connection techniques, incorporating auxiliary pull-up and pull-down networks to mitigate SEEs, virtually eliminating SETs and reducing error-rates by using PMOS and NMOS transistors in a split-logic configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistor up-sizing is used for radiation hardening, then reliability against SEEs is improved, but area and power consumption increase significantly
Solution Approach 1:
The circuit is divided into two stages: a first stage circuit that is virtually SET-free and a second stage circuit that drives the output. This segmentation allows the first stage to be optimized for radiation hardness with minimal area, while the second stage handles the driving function, avoiding the need to up-size all transistors for radiation protection.
Solution Approach 2:
A coupling network is introduced as an intermediary between the first and second stage circuits. This coupling network transfers signals from the radiation-hardened first stage to the output-driving second stage, allowing the benefits of radiation hardening to be achieved without requiring the entire circuit to be up-sized.
2Reliability
If transistor up-sizing is used for radiation hardening, then reliability against SEEs is improved, but power consumption increases
Solution Approach 1:
The circuit is divided into two stages: a first stage circuit that is virtually SET-free and a second stage circuit that drives the output. This segmentation allows the first stage to be optimized for radiation hardness with minimal area, while the second stage handles the driving function, avoiding the need to up-size all transistors for radiation protection.
Solution Approach 2:
A coupling network is introduced as an intermediary between the first and second stage circuits. This coupling network transfers signals from the radiation-hardened first stage to the output-driving second stage, allowing the benefits of radiation hardening to be achieved without requiring the entire circuit to be up-sized.
3Ease of manufacture
If conventional IC fabrication processes are used, then manufacturing cost and availability are improved, but radiation hardness is insufficient
Solution Approach 1:
The invention changes the circuit topology and configuration parameters rather than relying on specialized fabrication processes. By using standard CMOS processes with modified circuit arrangements (two-stage structure with specific coupling), radiation hardness is achieved through design rather than manufacturing, making the process widely available and cost-effective.
Solution Approach 2:
The invention replaces the physical/manufacturing-based radiation hardening approach (specialized fabrication processes) with a circuit-design-based approach. Instead of changing the physical manufacturing process, the solution uses electrical/circuit configuration (two-stage structure, coupling networks) to achieve radiation hardness, substituting a design mechanism for a manufacturing mechanism.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed technique achieves ultra-low error-rates in digital circuits, with error-rates 7× to 215× lower than non-RHBD designs and 2× to 74× lower than known RHBD up-sizing techniques, while maintaining compact diffusion areas and reducing power consumption.
Implementation Method 1
One of the SEEs is single-event-transient (SET) where a single event (e.g., an energized particle) striking at a transistor node induces electrical charges that create a transient pulse on the transistor node.
Data Source
Figure 1A~1C
Figure 1D~1F
Figure 2A~2D
AI summary
A circuit arrangement is provided, having a first circuit configured to receive an input signal, and a second circuit configured to provide an output signal, wherein the first circuit includes a first pull-up network having a first transistor of a first conductivity type and a second transistor of a second conductivity type electrically coupled to each other, and a first pull-down network having a first transistor of the first conductivity type and a second transistor of the second conductivity type electrically coupled to each other, wherein the second circuit includes a second pull-up network having a first transistor of the first conductivity type, and a second pull-down network having a second transistor of the second conductivity type, wherein the first pull-up network and the second pull-down network are electrically coupled to each other, and wherein the first pull-down network and the second pull-up network are electrically coupled to each other.