Two Stage Command Buffer for IOMMU Map Overlap
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Solution Overview
Problem
The existing process of writing data from second-tier memory devices, such as flash memory, to DRAM introduces significant latency due to the need for IOMMU mappings and serial data copying, which can be burdensome and time-consuming, especially when using input/output memory management units (IOMMU) that enforce the principle of least privilege.
Innovation Solution
The implementation of a two-stage command buffer system that overlaps IOMMU map-in operations with second-tier memory access, allowing data to be copied from the second-tier memory into a storage controller's internal buffer during the initial mapping phase, and then written to DRAM during the second stage, thereby reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If IOMMU mappings are dynamically created for each write operation from second tier memory to DRAM, then security and memory protection are maintained, but significant latency is introduced due to the serial mapping and copying process
Solution Approach 1:
The system pre-creates IOMMU mappings in advance before data transfer is needed. When data is written to second tier memory, the corresponding IOMMU mapping is established beforehand, allowing the subsequent read and copy operations to proceed without mapping delays. This preliminary action eliminates the critical path latency caused by dynamic mapping creation during data transfer operations.
Solution Approach 2:
The data transfer process is segmented into independent stages: mapping creation, data read from second tier memory, and copy to DRAM. By using multiple command buffers (first buffer for mapping, second buffer for data transfer), the system can overlap these stages, allowing mapping to occur in parallel with data reading, thereby reducing total latency while maintaining security.
2Reliability
If serial copying process is used from second tier memory through internal buffer to DRAM, then data integrity and security are maintained, but transfer speed is significantly reduced
Solution Approach 1:
The system maintains continuous useful action by overlapping the mapping creation process with the data read process using separate command buffers. While the first command buffer handles mapping establishment, the second command buffer simultaneously performs the data read from second tier memory. This continuity eliminates idle waiting time between sequential operations, significantly improving transfer speed while maintaining data integrity through controlled access paths.
Data Source
AI summary
IOMMU map-in may be overlapped with second tier memory access, such that the two operations are at least partially performed at the same time. For example, when a second tier memory read into a storage device controller internal buffer is initiated, an IOMMU mapping may be built simultaneously. To achieve this overlap, a two-stage command buffer is used. In a first stage, content is read from a second tier memory address into the storage device controller internal buffer. In a second stage, the internal buffer is written into the DRAM physical address.