Two-Stage Data Serialization With Delayed Quadrature Clock
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Solution Overview
Problem
Existing system-on-chip (SOC) devices face challenges in efficiently serializing data between chiplets due to increased power consumption and bandwidth degradation when implementing 4:1 muxes at the transmission driver circuitry.
Innovation Solution
A two-stage data serialization approach is implemented, using first multiplexing circuitry to partially serialize a data group into subgroups based on an in-phase clock and delay a quadrature clock, followed by second multiplexing circuitry with a source-series terminated (SST) driver to serialize the subgroups into a serial data stream based on the delayed quadrature clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If 4:1 muxes are implemented at the transmission driver circuitry, then data serialization capability is improved, but power consumption increases
Solution Approach 1:
The patent divides the single 4:1 mux function into two separate 2:1 mux stages. The first 2:1 mux performs initial serialization of four data bits into two intermediate signals, and the second 2:1 mux further serializes these into the final serial stream. This segmentation reduces the complexity and power consumption of individual mux circuits while achieving the same overall 4:1 serialization function.
2Productivity
If 4:1 muxes are implemented at the transmission driver circuitry, then data serialization capability is improved, but bandwidth degradation occurs
Solution Approach 1:
By splitting the 4:1 mux into two 2:1 mux stages, each operating at a lower data rate, the patent reduces bandwidth degradation. The first 2:1 mux operates on grouped bits, and the second 2:1 mux operates on the intermediate results, allowing each stage to maintain better signal integrity and reduce cumulative bandwidth loss compared to a single high-ratio mux.
Solution Approach 2:
The patent introduces intermediate signaling and clock management between the two mux stages. The first mux produces intermediate serialized data that is then processed by the second mux, with appropriate clock timing and signal conditioning in between. This intermediary processing allows each stage to operate more efficiently and reduces overall bandwidth degradation.
3Device complexity
If single-stage 4:1 serialization is used, then device complexity is reduced, but power consumption and bandwidth degradation increase
Solution Approach 1:
The patent applies segmentation by dividing the serialization function into two manageable 2:1 mux stages rather than one complex 4:1 mux. While this increases the number of components, each stage is simpler to implement and optimize, leading to reduced power consumption and better bandwidth performance that compensates for the increased structural complexity.
Data Source
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AI summary
A transmission driver for serial communication includes first multiplexing circuitry configured to partially serialize a data group into data subgroups based on an in-phase clock, and to delay a quadrature clock corresponding to the in-phase clock. The delay is based on latency of the partial serialization. The transmission driver also includes second multiplexing circuitry having a source-series terminated (SST) driver configured to serialize the data subgroups into a serial data stream based on the delayed quadrature clock. The first multiplexing circuitry may be configured to partially serialize the data group into the data subgroups by arranging a four-bit data group into a pair of two-bit data groups, and the second multiplexing circuitry may be configured to serialize the data subgroups into the serial data stream by arranging the pair of two-bit data groups into the serial data stream.