Two-Stage Data Transfer System Minimizing RMW Operations
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing data transfer techniques, such as those involving DMA controllers, are inefficient when dealing with multiple I/O devices from different vendors, leading to frequent read-modify-write (RMW) operations and performance deterioration due to varying data transfer characteristics, requiring dedicated DMA controllers for each device and increasing system complexity.
Innovation Solution
A two-stage data transfer system is implemented, where an accelerator interposed between I/O devices and main storage memory absorbs differences in data transfer characteristics by temporarily storing data in an accelerator memory and then transferring it in optimal units, minimizing RMW occurrences without adding dummy data or dedicated DMA controllers for each device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dummy data is added to match data width units for DMA transfer, then data transfer performance is improved, but data may be destroyed (overwritten) by subsequent dummy data transfers
Solution Approach 1:
The patent introduces an intermediary buffer memory that temporarily stores data before DMA transfer. This buffer acts as a mediator between the data source and destination, allowing the system to track and manage data transfer boundaries without adding dummy data, thereby preventing data overwrite while maintaining transfer efficiency.
Solution Approach 2:
The patent dynamically adjusts transfer parameters including data width, transfer size, and alignment based on the actual data characteristics and buffer status. By changing these parameters adaptively rather than using fixed dummy data padding, the system achieves efficient transfer without compromising data integrity.
2Adaptability or versatility
If a dedicated DMA controller is used for each I/O device to handle varying data transfer characteristics, then data transfer compatibility is improved, but system complexity and component count increase
Solution Approach 1:
The patent implements a universal DMA controller that can handle multiple I/O devices with different data transfer characteristics through a common interface. The controller adapts to various device requirements by dynamically adjusting transfer parameters and using a standardized buffer memory structure, eliminating the need for dedicated controllers for each device.
Solution Approach 2:
The patent segments the data transfer process into standardized stages: data reception from I/O devices into buffer memory, parameter analysis, and DMA transfer to destination. This segmentation allows a single DMA controller to efficiently manage multiple devices by processing each transfer through the same modular stages with device-specific parameter adjustments.
3Reliability
If static mode switching is used to avoid dummy data overwriting, then data integrity is maintained, but transfer efficiency decreases due to mode switching overhead
Solution Approach 1:
The patent employs dynamic parameter adjustment rather than static mode switching. The system continuously monitors data characteristics and buffer status, then adaptively changes transfer parameters including data width, alignment, and transfer size in real-time. This dynamic approach maintains data integrity while optimizing transfer efficiency without the overhead of mode switching.
Data Source
AI summary
A data transfer system including a first memory and a processor includes a second memory and a DMA controller. The processor performs RMW on data which has a size less than a cache line size and in which a portion of a cache line (a unit area of the first memory) is a write destination. Output target data is transferred from an I/O device to the second memory. Thereafter, the DMA controller transfers the output target data from the second memory to the first memory in one or a plurality of transfer unit sizes by which the number of occurrences of RMW is minimized.