Two-Stage DFE Circuit for Lower-Power Serial Data Reduction
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Solution Overview
Problem
High-speed serial data receivers in integrated circuits face challenges with high power consumption when operating at high clock rates, necessitating a low-power solution for data rate reduction, as current half-rate or quarter-rate decision feedback equalizers using current mode logic exhibit high power consumption.
Innovation Solution
A two-stage decision feedback equalizer is implemented, comprising a half-rate predictive decision feedback equalizer stage using current mode logic and a quarter-rate stage using complementary metal oxide semiconductor circuits, operating at different clock frequencies to reduce power consumption and align clock phases effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a half-rate or quarter-rate decision feedback equalizer is implemented using current mode logic, then the data rate reduction function is achieved, but the power consumption becomes relatively high
Solution Approach 1:
The patent divides the decision feedback equalizer into multiple stages, with the first stage operating at half-rate and the second stage operating at quarter-rate. This segmentation allows each stage to operate at optimized clock frequencies, reducing overall power consumption while maintaining the required data rate reduction functionality.
Solution Approach 2:
The patent employs dynamic clocking where different stages operate at different clock domains (first clock domain for half-rate, second clock domain for quarter-rate). This dynamic approach allows the circuit to adapt its operating frequency to the specific requirements of each processing stage, thereby reducing power consumption compared to a uniform high-speed operation.
2Use of energy by moving object
If CMOS circuits are used for the second stage operating at quarter-rate, then power consumption is reduced, but the circuit complexity increases due to multi-clock domain synchronization requirements
Solution Approach 1:
The patent introduces a phase control circuit as an intermediary mechanism to synchronize the first and second clock domains. This phase control circuit manages the complexity of multi-clock domain operation by providing controlled phase alignment between the half-rate and quarter-rate clock signals, enabling the CMOS circuits to operate efficiently while maintaining system coherence.
Solution Approach 2:
The patent changes the operational parameters of different stages by assigning them to different clock domains with different frequencies. The first stage operates in a first clock domain at half-rate, while the second stage operates in a second clock domain at quarter-rate. This parameter differentiation allows optimization of power consumption in the second stage while managing complexity through systematic clock domain separation.
Data Source
AI summary
A two-stage decision feedback equalizer. The decision feedback equalizer is configured to receive serial data, at an analog input, at a first data rate. The two-stage decision feedback equalizer has an analog input and four digital outputs, and includes a first stage and a second stage. The first stage is connected to the analog input, and includes a half-rate predictive decision feedback equalizer consisting of current mode logic circuits. The second stage is connected to the first stage, and consists of complementary metal oxide semiconductor circuits.