Two-Stage ESD Clamp Circuit for Low-Leakage Negative Voltage Swings
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Solution Overview
Problem
Conventional ESD protection circuits for semiconductor devices with smaller transistors, such as those using 5 or sub-5 nm finFET technology, struggle to handle the increased voltage swing requirements due to smaller operating voltages, leading to reduced fail-safe voltage specifications and significant damage from current leakage.
Innovation Solution
The implementation of a semiconductor device with an ESD circuitry that includes a parasitic bipolar junction transistor (BJT) structure with back-to-back diodes and a dual clamp arrangement, which shunts both positive and negative currents effectively, combined with a two-stage ultra-low leakage implementation using a PD mode clamp and an RC-MOS clamp, to handle larger voltage swings and reduce leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ESD protection circuits are used for smaller transistors, then the circuit structure is simple, but the voltage swing handling capability is insufficient and leakage current is high
Solution Approach 1:
The ESD protection circuit is divided into two distinct stages: a first-stage ESD clamp circuit for initial ESD event response, and a second-stage ESD clamp circuit for follow-up protection. This segmentation allows each stage to be optimized independently - the first stage handles large voltage swings while the second stage provides low-leakage protection, resolving the contradiction between protection capability and leakage reduction without requiring a monolithic complex circuit
Solution Approach 2:
The patent combines multiple protection mechanisms into a unified two-stage system: parasitic BJT structures with back-to-back diodes in the first stage, and RC-MOS clamp circuits in the second stage. By merging these different protection approaches in series, the circuit achieves both high voltage swing handling capability and low leakage current, while the shared power ground interconnect structure further integrates the design
2Adaptability or versatility
If ESD clamps are designed for larger voltage swings, then the voltage swing handling capability increases, but the standby current leakage increases significantly
Solution Approach 1:
The two-stage ESD clamp circuit provides dynamic protection response: during ESD events with large voltage swings, the first-stage clamp activates to handle the high-voltage transient, while during normal operation the second-stage clamp maintains low leakage. This dynamic switching between protection modes resolves the contradiction between voltage swing handling and leakage reduction
Solution Approach 2:
The patent introduces an intermediate RC-MOS clamp circuit between the input-output pads and the core logic circuitry. This intermediary second-stage clamp acts as a buffer that limits leakage current to less than 5 nA during standby while still providing ESD protection, mediating between the high-voltage-swing first stage and the sensitive core circuitry
3Area of moving object
If smaller transistors are used to reduce device size, then the device footprint decreases, but the voltage swing range that needs to be handled increases
Solution Approach 1:
The patent applies different protection characteristics to different parts of the circuit: the first-stage ESD clamp with parasitic BJT structures is optimized for high-voltage-swing handling to protect against ESD events, while the second-stage ESD clamp with RC-MOS circuits is optimized for low-leakage operation during normal small-signal conditions. This local differentiation allows small transistors to be used in the core logic while maintaining robust ESD protection at the I/O interfaces
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides enhanced ESD protection for smaller transistors by effectively handling voltage swings up to +/−2.5V, reducing standby current leakage to less than 5 nA, and minimizing latch-up susceptibility while reducing the footprint by up to 20% compared to conventional solutions.
Implementation Method 1
The ESD clamp may comprise a parasitic bipolar junction transistor (BJT) circuit structure that comprises back to back (or anti-parallel) diodes
Implementation Method 2
The parasitic BJT circuit structure may comprise a collector terminal and an emitter terminal, wherein a third diode may be coupled in series to the BJT circuit structure
Implementation Method 3
ESD protection clamp circuits are used to prevent component damage on the integrated circuits of the semiconductor devices. The ESD clamps shunt ESD currents
Data Source
AI summary
An electrostatic discharge protection circuit, device, system, and apparatus has low-leakage for a large voltage swing of negative current.