Two-Stage Converter Control With Sub-10 μs Fault Synchronization
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Solution Overview
Problem
Incoordination between different modules in an electrical system leads to decreased system reliability due to communication latency between digital signal processors, resulting in delayed protection actions and potential device damage.
Innovation Solution
Establish a low-latency data interaction channel using output crossbar switches and additional hardware circuits between digital signal processors, along with isolation modules and redundant signal paths, to quickly transmit fault signals and ensure synchronized protection actions across conversion modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional communication channels are used between digital signal processors, then device complexity is reduced, but the time interval for triggering protection actions increases and system reliability deteriorates
Solution Approach 1:
The communication channel is segmented into multiple paths: a high-speed direct connection path for critical fault signals and a standard communication path for normal operations. This segmentation allows the system to use different communication methods depending on the urgency of the signal, resolving the contradiction between speed and complexity.
Solution Approach 2:
An intermediary hardware circuit is introduced between the digital signal processors to facilitate rapid signal transmission. This intermediary component acts as a dedicated communication channel that bypasses traditional software-based communication protocols, enabling sub-10μs response times while maintaining system reliability.
2Reliability
If standard communication protocols are used between modules, then device complexity is minimized, but coordination between modules deteriorates and protection actions are delayed
Solution Approach 1:
The communication system dynamically switches between different transmission modes based on signal priority. Normal operational signals use standard communication protocols, while fault signals automatically route through the high-speed direct connection. This dynamic adaptation resolves the contradiction by optimizing the communication channel structure according to real-time needs.
Solution Approach 2:
The high-speed communication path is pre-configured and ready before faults occur. The hardware circuit is designed in advance to provide a dedicated route for critical signals, eliminating the need for complex runtime decision-making and ensuring immediate response when faults are detected.
3Reliability
If digital signal processors operate independently, then device complexity is reduced, but incoordination between modules increases and system reliability deteriorates
Solution Approach 1:
A feedback mechanism is implemented where the second digital signal processor receives fault signals from the first processor and responds by triggering protective actions. This closed-loop feedback ensures coordination between independently operating processors, resolving the contradiction between simplicity and reliability.
Data Source
AI summary
This application discloses an electrical system and an electrical apparatus. The electrical system includes: a first-stage conversion module including a plurality of first controllable switches; a second-stage conversion module including a plurality of second controllable switches; a first digital signal processor configured to control the first controllable switch; and a second digital signal processor configured to control the second controllable switch, where a first output crossbar switch of the first digital signal processor is configured to supply a first internal signal to a first output port, so that the second digital signal processor receives the first internal signal within a preset time through a second input port. The internal signal of the first digital signal processor can be enabled to be transmitted to the second digital signal processor within a relatively short time, thereby reducing a time interval for triggering a protection action between the two digital signal processors.