Two-Stage Flash Cache Main Memory for Lower DRAM Cost and Power
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Solution Overview
Problem
The increasing demand for larger main memory in computing systems due to higher latency and cost of traditional DRAMs, which limits performance and power efficiency, and the need for instant response times in program execution.
Innovation Solution
Implementing a two-stage Flash-based Level Cache (FLC) system with a high-speed first FLC module and a lower-cost second FLC module, coupled with a storage drive partitioned for main memory, to virtualize main memory using predictive fetching and caching techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional DRAMs are used for main memory, then memory access speed is improved, but cost and power consumption increase
Solution Approach 1:
The patent segments memory into two distinct parts: a smaller, faster DRAM portion for active data and a larger, slower flash memory portion for inactive data. This segmentation allows the system to optimize for both speed (using DRAM when needed) and power efficiency (using flash for bulk storage), resolving the contradiction between access speed and power consumption.
Solution Approach 2:
The patent changes the operational parameters of the memory system by introducing a hybrid architecture that dynamically switches between DRAM and flash memory based on data access patterns. This parameter change enables the system to achieve lower average power consumption while maintaining acceptable access speeds through intelligent data placement and retrieval strategies.
2Quantity of substance
If DRAM storage capacity is increased, then main memory size is improved, but cost increases
Solution Approach 1:
The patent merges two different memory technologies (DRAM and flash memory) into a unified hybrid memory system. This combination allows the system to achieve large effective memory capacity using cost-effective flash memory while retaining the performance benefits of DRAM for frequently accessed data, thereby reducing overall cost while maintaining large memory size.
Solution Approach 2:
The patent introduces a memory management intermediary that mediates between the CPU and the hybrid storage system. This intermediary intelligently manages data placement between DRAM and flash memory, enabling the system to provide large memory capacity at lower cost by automatically handling data migration and access coordination without requiring expensive high-capacity DRAM.
3Quantity of substance
If DRAM storage capacity is increased, then main memory size is improved, but power consumption increases
Solution Approach 1:
The patent segments memory into two distinct parts: a smaller, faster DRAM portion for active data and a larger, slower flash memory portion for inactive data. This segmentation allows the system to optimize for both speed (using DRAM when needed) and power efficiency (using flash for bulk storage), resolving the contradiction between access speed and power consumption.
Solution Approach 2:
The patent changes the operational parameters of the memory system by introducing a hybrid architecture that dynamically switches between DRAM and flash memory based on data access patterns. This parameter change enables the system to achieve lower average power consumption while maintaining acceptable access speeds through intelligent data placement and retrieval strategies.
4Loss of time
If cache size is increased, then memory access latency is improved, but device complexity increases
Solution Approach 1:
The patent extracts the bulk storage function from the traditional DRAM main memory and places it in flash memory, which is managed by a memory management intermediary. This extraction allows the system to use smaller, simpler DRAM caches for active data while offloading capacity requirements to the external flash storage, thereby reducing device complexity while maintaining low access latency for frequently used data.
Data Source
AI summary
A data access system including a processor, multiple cache modules for the main memory, and a storage drive. The cache modules include a FLC controller and a main memory cache. The multiple cache modules function as main memory. The processor sends read/write requests (with physical address) to the cache module. The cache module includes two or more stages with each stage including a FLC controller and DRAM (with associated controller). If the first stage FLC module does not include the physical address, the request is forwarded to a second stage FLC module. If the second stage FLC module does not include the physical address, the request is forwarded to the storage drive, a partition reserved for main memory. The first stage FLC module has high speed, lower power operation while the second stage FLC is a low-cost implementation. Multiple FLC modules may connect to the processor in parallel.